As detailed in https://lore.kernel.org/qemu-devel/174595764300.3422.1315646555350585183...@git.sr.ht/
there's an issue with an unaligned access that falls off the end of the last page. To solve this, we need to know about the state of the cpu, so add a new target hook. There are arguments to the hook that are currently unused, but would appear to come in handy for AArch64 v9.5 FEAT_CPA2, which we do not yet implement. r~ Richard Henderson (12): accel/tcg: Add TCGCPUOps.pointer_wrap target: Use cpu_pointer_wrap_notreached for strict align targets target: Use cpu_pointer_wrap_uint32 for 32-bit targets target/arm: Fill in TCGCPUOps.pointer_wrap target/i386: Fill in TCGCPUOps.pointer_wrap target/loongarch: Fill in TCGCPUOps.pointer_wrap target/mips: Fill in TCGCPUOps.pointer_wrap target/ppc: Fill in TCGCPUOps.pointer_wrap target/riscv: Fill in TCGCPUOps.pointer_wrap target/s390x: Fill in TCGCPUOps.pointer_wrap target/sparc: Fill in TCGCPUOps.pointer_wrap accel/tcg: Assert TCGCPUOps.pointer_wrap is set include/accel/tcg/cpu-ops.h | 13 +++++++++++++ accel/tcg/cpu-exec.c | 1 + accel/tcg/cputlb.c | 22 ++++++++++++++++++++++ target/alpha/cpu.c | 1 + target/arm/cpu.c | 24 ++++++++++++++++++++++++ target/arm/tcg/cpu-v7m.c | 1 + target/avr/cpu.c | 6 ++++++ target/hppa/cpu.c | 1 + target/i386/tcg/tcg-cpu.c | 7 +++++++ target/loongarch/cpu.c | 7 +++++++ target/m68k/cpu.c | 1 + target/microblaze/cpu.c | 1 + target/mips/cpu.c | 9 +++++++++ target/openrisc/cpu.c | 1 + target/ppc/cpu_init.c | 7 +++++++ target/riscv/tcg/tcg-cpu.c | 26 ++++++++++++++++++++++++++ target/rx/cpu.c | 1 + target/s390x/cpu.c | 9 +++++++++ target/sh4/cpu.c | 1 + target/sparc/cpu.c | 13 +++++++++++++ target/tricore/cpu.c | 1 + target/xtensa/cpu.c | 1 + 22 files changed, 154 insertions(+) -- 2.43.0
