Hi Jonathan and Alex.
(This patch is now merged as commit 1478b560902).
On 12/7/24 14:24, Jonathan Cameron via wrote:
Approach copied from gen_pcie_root_port.c
Previously the link defaulted to a maximum of 2.5GT/s and 1x. Enable setting
it's maximum values. The actual value after 'training' will depend on the
downstream device configuration.
Signed-off-by: Jonathan Cameron <jonathan.came...@huawei.com>
---
hw/pci-bridge/cxl_root_port.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/hw/pci-bridge/cxl_root_port.c b/hw/pci-bridge/cxl_root_port.c
index 2dd10239bd..5e2156d7ba 100644
--- a/hw/pci-bridge/cxl_root_port.c
+++ b/hw/pci-bridge/cxl_root_port.c
@@ -24,6 +24,7 @@
#include "hw/pci/pcie_port.h"
#include "hw/pci/msi.h"
#include "hw/qdev-properties.h"
+#include "hw/qdev-properties-system.h"
#include "hw/sysbus.h"
#include "qapi/error.h"
#include "hw/cxl/cxl.h"
@@ -206,6 +207,10 @@ static Property gen_rp_props[] = {
-1),
DEFINE_PROP_SIZE("pref64-reserve", CXLRootPort, res_reserve.mem_pref_64,
-1),
+ DEFINE_PROP_PCIE_LINK_SPEED("x-speed", PCIESlot,
+ speed, PCIE_LINK_SPEED_64),
+ DEFINE_PROP_PCIE_LINK_WIDTH("x-width", PCIESlot,
+ width, PCIE_LINK_WIDTH_32),
Per the documentation:
We commonly use a ``x-`` command name prefix to make lack of
stability obvious to human users.
Are these properties meant to be stable? You mentioned "Approach
copied from gen_pcie_root_port.c". There they were added because
of:
commit c2a490e344b4e231cf9488c67df7ee46977b1ebe
Author: Alex Williamson <alex.william...@redhat.com>
Date: Wed Dec 12 12:39:43 2018 -0700
pcie: Allow generic PCIe root port to specify link speed and width
Allow users to experimentally specify speed and width values for the
generic PCIe root port. Defaults remain at 2.5GT/s & x1 for
compatiblity with the intent to only support changing defaults via
machine types for now.
This was 6 years ago, are we still experimenting?
DEFINE_PROP_END_OF_LIST()
};
