There is no point in pushing this burden to the devices, they may rather
forget to call them (like intel-hda, ahci, xhci did). Instead, reset
functions are now called from pci_device_reset and pci_bridge_reset.
They do nothing if MSI/MSI-X is not in use.
CC: Alexander Graf <ag...@suse.de>
CC: Gerd Hoffmann <kra...@redhat.com>
CC: Isaku Yamahata <yamah...@valinux.co.jp>
Signed-off-by: Jan Kiszka <jan.kis...@siemens.com>
---
hw/ide/ich.c | 1 -
hw/intel-hda.c | 3 ---
hw/ioh3420.c | 2 +-
hw/pci.c | 5 +++++
hw/pci_bridge.c | 4 ++++
hw/usb/hcd-xhci.c | 1 -
hw/virtio-pci.c | 1 -
hw/xio3130_downstream.c | 2 +-
hw/xio3130_upstream.c | 2 +-
9 files changed, 12 insertions(+), 9 deletions(-)
diff --git a/hw/ide/ich.c b/hw/ide/ich.c
index e7026bb..d3bc822 100644
--- a/hw/ide/ich.c
+++ b/hw/ide/ich.c
@@ -88,7 +88,6 @@ static void pci_ich9_reset(DeviceState *dev)
{
struct AHCIPCIState *d = DO_UPCAST(struct AHCIPCIState, card.qdev, dev);
- msi_reset(&d->card);
ahci_reset(&d->ahci);
}
diff --git a/hw/intel-hda.c b/hw/intel-hda.c
index e38861e..bb11af2 100644
--- a/hw/intel-hda.c
+++ b/hw/intel-hda.c
@@ -1107,9 +1107,6 @@ static void intel_hda_reset(DeviceState *dev)
DeviceState *qdev;
HDACodecDevice *cdev;
- if (d->msi) {
- msi_reset(&d->pci);
- }
intel_hda_regs_reset(d);
d->wall_base_ns = qemu_get_clock_ns(vm_clock);
diff --git a/hw/ioh3420.c b/hw/ioh3420.c
index 1632d31..d1499da 100644
--- a/hw/ioh3420.c
+++ b/hw/ioh3420.c
@@ -81,7 +81,7 @@ static void ioh3420_write_config(PCIDevice *d,
static void ioh3420_reset(DeviceState *qdev)
{
PCIDevice *d = PCI_DEVICE(qdev);
- msi_reset(d);
+
ioh3420_aer_vector_update(d);
pcie_cap_root_reset(d);
pcie_cap_deverr_reset(d);
diff --git a/hw/pci.c b/hw/pci.c
index b706e69..2148245 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -31,6 +31,8 @@
#include "loader.h"
#include "range.h"
#include "qmp-commands.h"
+#include "msi.h"
+#include "msix.h"
//#define DEBUG_PCI
#ifdef DEBUG_PCI
@@ -188,6 +190,9 @@ void pci_device_reset(PCIDevice *dev)
}
}
pci_update_mappings(dev);
+
+ msi_reset(dev);
+ msix_reset(dev);
}
/*
diff --git a/hw/pci_bridge.c b/hw/pci_bridge.c
index 866f0b6..b533574 100644
--- a/hw/pci_bridge.c
+++ b/hw/pci_bridge.c
@@ -32,6 +32,8 @@
#include "pci_bridge.h"
#include "pci_internals.h"
#include "range.h"
+#include "msi.h"
+#include "msix.h"
/* PCI bridge subsystem vendor ID helper functions */
#define PCI_SSVID_SIZEOF 8
@@ -296,6 +298,8 @@ void pci_bridge_reset(DeviceState *qdev)
{
PCIDevice *dev = PCI_DEVICE(qdev);
pci_bridge_reset_reg(dev);
+ msi_reset(dev);
+ msix_reset(dev);
}
/* default qdev initialization function for PCI-to-PCI bridge */
diff --git a/hw/usb/hcd-xhci.c b/hw/usb/hcd-xhci.c
index 814117c..7550412 100644
--- a/hw/usb/hcd-xhci.c
+++ b/hw/usb/hcd-xhci.c
@@ -2343,7 +2343,6 @@ static void xhci_reset(DeviceState *dev)
{
XHCIState *xhci = DO_UPCAST(XHCIState, pci_dev.qdev, dev);
- msi_reset(&xhci->pci_dev);
xhci_reset_full(xhci);
}
diff --git a/hw/virtio-pci.c b/hw/virtio-pci.c
index 4a4413d..3395a02 100644
--- a/hw/virtio-pci.c
+++ b/hw/virtio-pci.c
@@ -277,7 +277,6 @@ void virtio_pci_reset(DeviceState *d)
VirtIOPCIProxy *proxy = container_of(d, VirtIOPCIProxy, pci_dev.qdev);
virtio_pci_stop_ioeventfd(proxy);
virtio_reset(proxy->vdev);
- msix_reset(&proxy->pci_dev);
proxy->flags &= ~VIRTIO_PCI_FLAG_BUS_MASTER_BUG;
}
diff --git a/hw/xio3130_downstream.c b/hw/xio3130_downstream.c
index 319624f..3716e45 100644
--- a/hw/xio3130_downstream.c
+++ b/hw/xio3130_downstream.c
@@ -48,7 +48,7 @@ static void xio3130_downstream_write_config(PCIDevice *d,
uint32_t address,
static void xio3130_downstream_reset(DeviceState *qdev)
{
PCIDevice *d = PCI_DEVICE(qdev);
- msi_reset(d);
+
pcie_cap_deverr_reset(d);
pcie_cap_slot_reset(d);
pcie_cap_ari_reset(d);
diff --git a/hw/xio3130_upstream.c b/hw/xio3130_upstream.c
index 34a99bb..962d48e 100644
--- a/hw/xio3130_upstream.c
+++ b/hw/xio3130_upstream.c
@@ -47,7 +47,7 @@ static void xio3130_upstream_write_config(PCIDevice *d,
uint32_t address,
static void xio3130_upstream_reset(DeviceState *qdev)
{
PCIDevice *d = PCI_DEVICE(qdev);
- msi_reset(d);
+
pci_bridge_reset(qdev);
pcie_cap_deverr_reset(d);
}
--
1.7.3.4
