On 4/30/25 12:30, Kane Chen wrote:
Hi Cédric,
Currently, the OTP memory is not supported, but the guest firmware
still attempts to access it, even though no functionality is
available.
To handle this case, I will silently discard those operations when no
backend is present, so that the machine can still boot and run without
error.
If you would prefer to have a message logged, please let me know.
Please add trace events for this case. There are always useful.
Thanks,
C.
Best Regards,
Kane
-----Original Message-----
From: Cédric Le Goater <c...@kaod.org>
Sent: Tuesday, April 29, 2025 5:06 PM
To: Kane Chen <kane_c...@aspeedtech.com>; Peter Maydell
<peter.mayd...@linaro.org>; Steven Lee <steven_...@aspeedtech.com>; Troy
Lee <leet...@gmail.com>; Jamin Lin <jamin_...@aspeedtech.com>; Andrew
Jeffery <and...@codeconstruct.com.au>; Joel Stanley <j...@jms.id.au>; open
list:ASPEED BMCs <qemu-...@nongnu.org>; open list:All patches CC here
<qemu-devel@nongnu.org>
Cc: Troy Lee <troy_...@aspeedtech.com>
Subject: Re: [PATCH v3 3/3] hw/arm: Integrate Aspeed OTP memory into
AST10x0 and AST2600 SoCs
Hello Kane,
[ ... ]
The Secure Boot Controller (SBC) includes some components like OTP
memory, crypto engine, boot controller, and so on. All components
within the SBC are fixed and cannot be changed. If we allow an otpmem
machine option, it may imply that different types or sizes of OTP
memory models are supported, such as:
* Different size: -M ast2600-evb,otpmem=otpmem-64k-drive
* Different model: -M ast2600-evb,otpmem=flash-drive
The optmem model should check the size and fail to realize in that case. This
would stop the machine before reset. This is a common pattern in QEMU. See
m25p80_realize().
Also, I think we would like the machine to start even if there is no block
backend. Please check how m25p80 models that behavior.
Thanks,
C.
