On Wed, Apr 30, 2025 at 08:26:23AM +0200, Philippe Mathieu-Daudé wrote: > Hi, > > On 13/2/25 13:37, Philippe Mathieu-Daudé wrote: > > +AMD folks > > > > On 12/2/25 23:01, Richard Henderson wrote: > > > Use out-of-line helpers to implement extended address memory ops. > > > With this, we can reduce TARGET_LONG_BITS to the more natural 32 > > > for this 32-bit cpu. > > > > I thought about something similar 2 months ago, but then realized > > MicroBlaze cores can be synthetized in 64-bit, and IIRC there is > > not much missing (I'd say effort would be to add 20% more of what > > we currently have). Just wanted to mention before taking the > > decision to restrict to 32-bit. OTOH if there are no plan for > > adding 64-bit support at AMD, then I'm more than happy to simplify > > by considering only 32-bit. > > I gave this series another go, and figured the microblaze target > addition was done way before the 64-bit. C_DATA_SIZE value was fixed > as 32, and C_ADDR_SIZE was not mentioned. Later C_DATA_SIZE became > configurable as [32, 64] and C_ADDR_SIZE appeared. > > Indeed what this series does is correctly implement the current > target as C_DATA_SIZE=32 (C_ADDR_SIZE=32 implied). > > I had a quick look at what is missing for C_DATA_SIZE > 32 and it > is more than the 20% I first roughly estimated. So with the current > implementation, this series is doing the right thing IMHO. >
Hi, Seems I lost track of this series. I agree that Richard's series looks good. At the time I may have had some idea of prepping for full 64bit support, I don't remember. If we ever add full 64bit support we can have have another look and see how it makes sense to change things. Cheers, Edgar
