> @@ -4212,7 +4213,8 @@ static const X86CPUDefinition builtin_x86_defs[] = { > VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | > VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | > VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | > - VMX_VM_EXIT_LOAD_IA32_EFER | > VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, > + VMX_VM_EXIT_LOAD_IA32_EFER | > VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | > + VMX_VM_EXIT_SAVE_IA32_PERF_GLOBAL_CTRL, > .features[FEAT_VMX_MISC] = > MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | > MSR_VMX_MISC_VMWRITE_VMEXIT, > @@ -4368,7 +4370,8 @@ static const X86CPUDefinition builtin_x86_defs[] = { > VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | > VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | > VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | > - VMX_VM_EXIT_LOAD_IA32_EFER | > VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, > + VMX_VM_EXIT_LOAD_IA32_EFER | > VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | > + VMX_VM_EXIT_SAVE_IA32_PERF_GLOBAL_CTRL, > .features[FEAT_VMX_MISC] = > MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | > MSR_VMX_MISC_VMWRITE_VMEXIT, > @@ -4511,7 +4514,8 @@ static const X86CPUDefinition builtin_x86_defs[] = { > VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | > VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | > VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | > - VMX_VM_EXIT_LOAD_IA32_EFER | > VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, > + VMX_VM_EXIT_LOAD_IA32_EFER | > VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | > + VMX_VM_EXIT_SAVE_IA32_PERF_GLOBAL_CTRL, > .features[FEAT_VMX_MISC] = > MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | > MSR_VMX_MISC_VMWRITE_VMEXIT,
Instead of modifying SPR's CPU model directly, we should introduce a new version (SapphireRapids-v4), like Skylake-Server-v4 enables "vmx-eptp-switching".