Re: [PATCH alternate 1/2] target/riscv: Update pc before csrw, csrrw

[Daniel Henrique Barboza]

On 4/25/25 1:50 PM, Richard Henderson wrote:

Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
---

Reviewed-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>

  target/riscv/insn_trans/trans_rvi.c.inc | 4 ++++
  1 file changed, 4 insertions(+)

diff --git a/target/riscv/insn_trans/trans_rvi.c.inc 
b/target/riscv/insn_trans/trans_rvi.c.inc
index b9c7160468..a367fecf7e 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -992,6 +992,7 @@ static bool do_csrw(DisasContext *ctx, int rc, TCGv src)
      TCGv_i32 csr = tcg_constant_i32(rc);

translator_io_start(&ctx->base);

+    gen_update_pc(ctx, 0);
      gen_helper_csrw(tcg_env, csr, src);
      return do_csr_post(ctx);
  }
@@ -1002,6 +1003,7 @@ static bool do_csrrw(DisasContext *ctx, int rd, int rc, 
TCGv src, TCGv mask)
      TCGv_i32 csr = tcg_constant_i32(rc);

translator_io_start(&ctx->base);

+    gen_update_pc(ctx, 0);
      gen_helper_csrrw(dest, tcg_env, csr, src, mask);
      gen_set_gpr(ctx, rd, dest);
      return do_csr_post(ctx);
@@ -1025,6 +1027,7 @@ static bool do_csrw_i128(DisasContext *ctx, int rc, TCGv 
srcl, TCGv srch)
      TCGv_i32 csr = tcg_constant_i32(rc);

translator_io_start(&ctx->base);

+    gen_update_pc(ctx, 0);
      gen_helper_csrw_i128(tcg_env, csr, srcl, srch);
      return do_csr_post(ctx);
  }
@@ -1037,6 +1040,7 @@ static bool do_csrrw_i128(DisasContext *ctx, int rd, int 
rc,
      TCGv_i32 csr = tcg_constant_i32(rc);

translator_io_start(&ctx->base);

+    gen_update_pc(ctx, 0);
      gen_helper_csrrw_i128(destl, tcg_env, csr, srcl, srch, maskl, maskh);
      tcg_gen_ld_tl(desth, tcg_env, offsetof(CPURISCVState, retxh));
      gen_set_gpr128(ctx, rd, destl, desth);