Hi,
In this second version the most noticeable changes are:
- patch "target/riscv/kvm: reset 'scounteren' with host val" was
dropped. After the v1 reviews [1] we decided that a better way would
be to change the default 'virt' CPU to max. This would prevent the
error condition handled in that patch to occur in the first place;
- we're not saving the size of the CPURISCVState flags that will be used
to store the KVM CSR regs. We'll write the flags directly;
- as a result of the aforementioned change, we're changing the size of
scounteren from uint32_t to target_ulong. All KVM CSRs are ulongs, and
we don't want to deal with a 64 bit CSR write into a 32 bit flag.
mcounteren was changed for consistency;
- scounteren requires the size change to be effective before KVM can use
it, so I've split the patch that introduced scounteren and senvcfg in
two.
Other minor changes after feedback from v1 were also made.
Patches based on alistair/riscv-to-apply.next branch with a build fix
(see [2] for more info).
Changes from v1:
- patch 7 ("target/riscv/kvm: reset 'scounteren' with host val")
- dropped
- patch 2 (new):
- fix mem leak
- patch 5 (former 4):
- kvm_cpu_csr_get_u32() now returns an uint32_t
- removed prop_size attribute from KVMCPUConfig
- use KVM_REG_SIZE to determine the read/write size of the CSR
- patch 6 (former 5):
- rename kvm_riscv_init_multiext_csr_cfg() to kvm_riscv_init_cfg()
- patch 7 (former 6):
- removed all tags
- added 'Reported-by' tag
- removed 'scounteren'
- patch 8 (new):
- change scounteren and mcounteren to 'target_ulong'
- patch 9 (new):
- add scounteren KVM CSR
- added 'Reported-by' tag
- v1 link:
https://lore.kernel.org/qemu-riscv/20250417124839.1870494-1-dbarb...@ventanamicro.com/
[1]
https://lore.kernel.org/qemu-riscv/20250417124839.1870494-1-dbarb...@ventanamicro.com/
[2]
https://lore.kernel.org/qemu-devel/8f3bae37-e1f3-4e55-9dc6-b7876992b...@ventanamicro.com/
Daniel Henrique Barboza (9):
target/riscv/kvm: minor fixes/tweaks
target/riscv/kvm: fix leak in kvm_riscv_init_multiext_cfg()
target/riscv/kvm: turn u32/u64 reg functions in macros
target/riscv/kvm: turn kvm_riscv_reg_id_ulong() in a macro
target/riscv/kvm: add kvm_csr_cfgs[]
target/riscv/kvm: do not read unavailable CSRs
target/riscv/kvm: add senvcfg CSR
target/riscv: widen (m|s)counteren to target_ulong
target/riscv/kvm: add scounteren CSR
target/riscv/cpu.h | 5 +-
target/riscv/kvm/kvm-cpu.c | 331 +++++++++++++++++++++++--------------
target/riscv/machine.c | 8 +-
3 files changed, 216 insertions(+), 128 deletions(-)
--
2.49.0
