On Thu, Apr 17, 2025 at 11:42 PM Paolo Bonzini <pbonz...@redhat.com> wrote: > > Hi Alistair, > > sorry for the stupid question—I am not sure whether you are going to give > reviewed-by to the remaining patches, and also whether you would like me to > submit the PR for this or not.
Sorry, just getting through a backlog. I have reviewed and applied the patches Alistair > > Thanks in advance > > Paolo > > Il ven 28 feb 2025, 11:27 Paolo Bonzini <pbonz...@redhat.com> ha scritto: >> >> As in v1, what I really wanted to achieve was removing RISC-V's >> use of .instance_post_init; that's because RISC-V operate with an >> opposite conception of .instance_post_init compared to everyone >> else: RISC-V wants to register properties there, whereas x86 and >> hw/pci-bridge/pcie_root_port.c want to set them. While it's possible >> to move RISC-V's code to instance_init, the others have to run after >> global properties have been set by device_post_init(). >> >> The way to get there is to make CPU definitions entirely declarative. >> Previously, multiple instance_init functions each override the properties >> that were set by the superclass, and the code used a mix of subclassing >> and direct invocation of other functions. Now, instead, after .class_init >> all the settings for each model are available in a RISCVCPUDef struct, >> and the result is copied into the RISCVCPU at .instance_init time. >> This is done with a single function that starts from the parent's >> RISCVCPUDef and applies the delta stored in the CPU's class_data. >> >> Apart from the small reduction in line count, one advantage is that >> more validation of the models can be done unconditionally at startup, >> instead of happening dynamically if a CPU model is chosen. >> >> Based-on: <20250218165757.554178-1-pbonz...@redhat.com> >> >> Paolo >> >> v1->v2: >> - merged "remove target/riscv: remove unused macro DEFINE_CPU" >> - max SATP mode refactoring moved to its own series >> - included a couple of Philippe's patches from his "const class_data" series >> - RISCVCPUDef initializers all declared as const >> >> Paolo Bonzini (20): >> target/riscv: introduce RISCVCPUDef >> target/riscv: store RISCVCPUDef struct directly in the class >> target/riscv: merge riscv_cpu_class_init with the class_base function >> target/riscv: move RISCVCPUConfig fields to a header file >> target/riscv: add more RISCVCPUDef fields >> target/riscv: convert abstract CPU classes to RISCVCPUDef >> target/riscv: do not make RISCVCPUConfig fields conditional >> target/riscv: convert profile CPU models to RISCVCPUDef >> target/riscv: convert bare CPU models to RISCVCPUDef >> target/riscv: convert dynamic CPU models to RISCVCPUDef >> target/riscv: convert SiFive E CPU models to RISCVCPUDef >> target/riscv: convert ibex CPU models to RISCVCPUDef >> target/riscv: convert SiFive U models to RISCVCPUDef >> target/riscv: th: make CSR insertion test a bit more intuitive >> target/riscv: generalize custom CSR functionality >> target/riscv: convert TT C906 to RISCVCPUDef >> target/riscv: convert TT Ascalon to RISCVCPUDef >> target/riscv: convert Ventana V1 to RISCVCPUDef >> target/riscv: convert Xiangshan Nanhu to RISCVCPUDef >> target/riscv: remove .instance_post_init >> >> Philippe Mathieu-Daudé (2): >> target/riscv: Declare RISCVCPUClass::misa_mxl_max as RISCVMXL >> target/riscv: Convert misa_mxl_max using GLib macros >> >> target/riscv/cpu-qom.h | 2 + >> target/riscv/cpu.h | 27 +- >> target/riscv/cpu_cfg.h | 160 +----- >> target/riscv/cpu_cfg_fields.h.inc | 165 ++++++ >> hw/riscv/boot.c | 2 +- >> target/riscv/cpu.c | 909 ++++++++++++++---------------- >> target/riscv/csr.c | 2 +- >> target/riscv/gdbstub.c | 6 +- >> target/riscv/kvm/kvm-cpu.c | 23 +- >> target/riscv/machine.c | 6 +- >> target/riscv/tcg/tcg-cpu.c | 10 +- >> target/riscv/th_csr.c | 30 +- >> target/riscv/translate.c | 2 +- >> 13 files changed, 632 insertions(+), 712 deletions(-) >> create mode 100644 target/riscv/cpu_cfg_fields.h.inc >> >> -- >> 2.48.1
