On Wed, Apr 23, 2025 at 07:46:52PM +0800, Zhao Liu wrote: > Date: Wed, 23 Apr 2025 19:46:52 +0800 > From: Zhao Liu <zhao1....@intel.com> > Subject: [RFC 00/10] i386/cpu: Cache CPUID fixup, Intel cache model & topo > CPUID enhencement > X-Mailer: git-send-email 2.34.1 > > Hi all, > > (Since patches 1 and 2 involve changes to x86 vendors other than Intel, > I have also cc'd friends from AMD and Zhaoxin.) > > These are the ones I was going to clean up a long time ago: > * Fixup CPUID 0x80000005 & 0x80000006 for Intel (and Zhaoxin now). > * Add cache model for Intel CPUs. > * Enable 0x1f CPUID leaf for specific Intel CPUs, which already have > this leaf on host by default. > > Overall, the enhancements to the Intel CPU models are still based on > feedback received over time, for a long time... > > I'll introduce my changes one by one in the order of importance as I > see it. (The doc update is missing in this version.) > > > Intel Cache Model > ================= > > AMD has supports cache model for a long time. And this feature strats > from the Eduardo's idea [1]. > > Unfortunately, Intel does not support this, and I have received some > feedback (from Tejus on mail list [2] and kvm forum, and from Jason).
I need to add more background: the legacy "host-cache-info" is becoming failing... On SRF, we have observed that it cannot accurately identify cache topology, so we have to use "smp-cache" to set the cache topology. However, once "host-cache-info" is disabled, we lose the cache info that matches the real silicon... Therefore, we can only add the cache model for the named CPU model.
