On Sun, Apr 6, 2025 at 5:03 PM Paolo Bonzini <pbonz...@redhat.com> wrote:
>
> Start from the top of the hierarchy: dynamic and vendor CPUs are just
> markers, whereas bare CPUs can have their instance_init function
> replaced by RISCVCPUDef.
>
> The only difference is that the maximum supported SATP mode has to
> be specified separately for 32-bit and 64-bit modes.
>
> Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> target/riscv/cpu.h | 1 +
> target/riscv/cpu.c | 93 ++++++++++++++++++++++------------------------
> 2 files changed, 46 insertions(+), 48 deletions(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index acaa49b979c..d247b9007a6 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -547,6 +547,7 @@ typedef struct RISCVCPUDef {
> int priv_spec;
> int32_t vext_spec;
> RISCVCPUConfig cfg;
> + bool bare;
> } RISCVCPUDef;
>
> /**
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 620641fbed6..002f5a15ba2 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -1482,8 +1482,8 @@ static void riscv_cpu_init(Object *obj)
> * for all CPUs. Each accelerator will decide what to do when
> * users disable them.
> */
> - RISCV_CPU(obj)->cfg.ext_zicntr = true;
> - RISCV_CPU(obj)->cfg.ext_zihpm = true;
> + RISCV_CPU(obj)->cfg.ext_zicntr = !mcc->def->bare;
> + RISCV_CPU(obj)->cfg.ext_zihpm = !mcc->def->bare;
>
> /* Default values for non-bool cpu properties */
> cpu->cfg.pmu_mask = MAKE_64BIT_MASK(3, 16);
> @@ -1506,36 +1506,6 @@ static void riscv_cpu_init(Object *obj)
> }
> }
>
> -static void riscv_bare_cpu_init(Object *obj)
> -{
> - RISCVCPU *cpu = RISCV_CPU(obj);
> -
> - /*
> - * Bare CPUs do not inherit the timer and performance
> - * counters from the parent class (see riscv_cpu_init()
> - * for info on why the parent enables them).
> - *
> - * Users have to explicitly enable these counters for
> - * bare CPUs.
> - */
> - cpu->cfg.ext_zicntr = false;
> - cpu->cfg.ext_zihpm = false;
> -
> - /* Set to QEMU's first supported priv version */
> - cpu->env.priv_ver = PRIV_VERSION_1_10_0;
> -
> - /*
> - * Support all available satp_mode settings. The default
> - * value will be set to MBARE if the user doesn't set
> - * satp_mode manually (see set_satp_mode_default()).
> - */
> -#ifndef CONFIG_USER_ONLY
> - set_satp_mode_max_supported(RISCV_CPU(obj),
> - riscv_cpu_mxl(&RISCV_CPU(obj)->env) == MXL_RV32 ?
> - VM_1_10_SV32 : VM_1_10_SV57);
> -#endif
> -}
> -
> typedef struct misa_ext_info {
> const char *name;
> const char *description;
> @@ -3106,6 +3076,7 @@ static void riscv_cpu_class_base_init(ObjectClass *c,
> void *data)
>
> if (data) {
> const RISCVCPUDef *def = data;
> + mcc->def->bare |= def->bare;
> if (def->misa_mxl_max) {
> assert(def->misa_mxl_max <= MXL_RV128);
> mcc->def->misa_mxl_max = def->misa_mxl_max;
> @@ -3259,6 +3230,19 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt,
> char *nodename)
> }), \
> }
>
> +#define DEFINE_ABSTRACT_RISCV_CPU(type_name, parent_type_name, ...) \
> + { \
> + .name = (type_name), \
> + .parent = (parent_type_name), \
> + .abstract = true, \
> + .class_data = (void*) &((const RISCVCPUDef) { \
> + .priv_spec = RISCV_PROFILE_ATTR_UNUSED, \
> + .vext_spec = RISCV_PROFILE_ATTR_UNUSED, \
> + .cfg.max_satp_mode = -1, \
> + __VA_ARGS__ \
> + }), \
> + }
> +
> #define DEFINE_PROFILE_CPU(type_name, misa_mxl_max_, initfn) \
> { \
> .name = (type_name), \
> @@ -3285,22 +3269,35 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> .class_init = riscv_cpu_common_class_init,
> .class_base_init = riscv_cpu_class_base_init,
> },
> - {
> - .name = TYPE_RISCV_DYNAMIC_CPU,
> - .parent = TYPE_RISCV_CPU,
> - .abstract = true,
> - },
> - {
> - .name = TYPE_RISCV_VENDOR_CPU,
> - .parent = TYPE_RISCV_CPU,
> - .abstract = true,
> - },
> - {
> - .name = TYPE_RISCV_BARE_CPU,
> - .parent = TYPE_RISCV_CPU,
> - .instance_init = riscv_bare_cpu_init,
> - .abstract = true,
> - },
> +
> + DEFINE_ABSTRACT_RISCV_CPU(TYPE_RISCV_DYNAMIC_CPU, TYPE_RISCV_CPU),
> + DEFINE_ABSTRACT_RISCV_CPU(TYPE_RISCV_VENDOR_CPU, TYPE_RISCV_CPU),
> + DEFINE_ABSTRACT_RISCV_CPU(TYPE_RISCV_BARE_CPU, TYPE_RISCV_CPU,
> + /*
> + * Bare CPUs do not inherit the timer and performance
> + * counters from the parent class (see riscv_cpu_init()
> + * for info on why the parent enables them).
> + *
> + * Users have to explicitly enable these counters for
> + * bare CPUs.
> + */
> + .bare = true,
> +
> + /* Set to QEMU's first supported priv version */
> + .priv_spec = PRIV_VERSION_1_10_0,
> +
> + /*
> + * Support all available satp_mode settings. By default
> + * only MBARE will be available if the user doesn't enable
> + * a mode manually (see riscv_cpu_satp_mode_finalize()).
> + */
> +#ifdef TARGET_RISCV32
> + .cfg.max_satp_mode = VM_1_10_SV32,
> +#else
> + .cfg.max_satp_mode = VM_1_10_SV57,
> +#endif
> + ),
> +
> #if defined(TARGET_RISCV32)
> DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, MXL_RV32,
> riscv_max_cpu_init),
> #elif defined(TARGET_RISCV64)
> --
> 2.49.0
>
