On Sun, Apr 6, 2025 at 5:04 PM Paolo Bonzini <pbonz...@redhat.com> wrote:
>
> Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 127 +++++++++++++++++++++------------------------
> 1 file changed, 60 insertions(+), 67 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 45bed28ea8a..616d89be17e 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -540,72 +540,6 @@ static void rv64_veyron_v1_cpu_init(Object *obj)
> #endif
> }
>
> -/* Tenstorrent Ascalon */
> -static void rv64_tt_ascalon_cpu_init(Object *obj)
> -{
> - CPURISCVState *env = &RISCV_CPU(obj)->env;
> - RISCVCPU *cpu = RISCV_CPU(obj);
> -
> - riscv_cpu_set_misa_ext(env, RVG | RVC | RVS | RVU | RVH | RVV);
> - env->priv_ver = PRIV_VERSION_1_13_0;
> -
> - /* Enable ISA extensions */
> - cpu->cfg.mmu = true;
> - cpu->cfg.vlenb = 256 >> 3;
> - cpu->cfg.elen = 64;
> - cpu->env.vext_ver = VEXT_VERSION_1_00_0;
> - cpu->cfg.rvv_ma_all_1s = true;
> - cpu->cfg.rvv_ta_all_1s = true;
> - cpu->cfg.misa_w = true;
> - cpu->cfg.pmp = true;
> - cpu->cfg.cbom_blocksize = 64;
> - cpu->cfg.cbop_blocksize = 64;
> - cpu->cfg.cboz_blocksize = 64;
> - cpu->cfg.ext_zic64b = true;
> - cpu->cfg.ext_zicbom = true;
> - cpu->cfg.ext_zicbop = true;
> - cpu->cfg.ext_zicboz = true;
> - cpu->cfg.ext_zicntr = true;
> - cpu->cfg.ext_zicond = true;
> - cpu->cfg.ext_zicsr = true;
> - cpu->cfg.ext_zifencei = true;
> - cpu->cfg.ext_zihintntl = true;
> - cpu->cfg.ext_zihintpause = true;
> - cpu->cfg.ext_zihpm = true;
> - cpu->cfg.ext_zimop = true;
> - cpu->cfg.ext_zawrs = true;
> - cpu->cfg.ext_zfa = true;
> - cpu->cfg.ext_zfbfmin = true;
> - cpu->cfg.ext_zfh = true;
> - cpu->cfg.ext_zfhmin = true;
> - cpu->cfg.ext_zcb = true;
> - cpu->cfg.ext_zcmop = true;
> - cpu->cfg.ext_zba = true;
> - cpu->cfg.ext_zbb = true;
> - cpu->cfg.ext_zbs = true;
> - cpu->cfg.ext_zkt = true;
> - cpu->cfg.ext_zvbb = true;
> - cpu->cfg.ext_zvbc = true;
> - cpu->cfg.ext_zvfbfmin = true;
> - cpu->cfg.ext_zvfbfwma = true;
> - cpu->cfg.ext_zvfh = true;
> - cpu->cfg.ext_zvfhmin = true;
> - cpu->cfg.ext_zvkng = true;
> - cpu->cfg.ext_smaia = true;
> - cpu->cfg.ext_smstateen = true;
> - cpu->cfg.ext_ssaia = true;
> - cpu->cfg.ext_sscofpmf = true;
> - cpu->cfg.ext_sstc = true;
> - cpu->cfg.ext_svade = true;
> - cpu->cfg.ext_svinval = true;
> - cpu->cfg.ext_svnapot = true;
> - cpu->cfg.ext_svpbmt = true;
> -
> -#ifndef CONFIG_USER_ONLY
> - set_satp_mode_max_supported(cpu, VM_1_10_SV57);
> -#endif
> -}
> -
> static void rv64_xiangshan_nanhu_cpu_init(Object *obj)
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> @@ -3217,7 +3151,66 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> #endif
> ),
>
> - DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_TT_ASCALON, MXL_RV64,
> rv64_tt_ascalon_cpu_init),
> + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_TT_ASCALON, TYPE_RISCV_VENDOR_CPU,
> + .misa_mxl_max = MXL_RV64,
> + .misa_ext = RVG | RVC | RVS | RVU | RVH | RVV,
> + .priv_spec = PRIV_VERSION_1_13_0,
> + .vext_spec = VEXT_VERSION_1_00_0,
> +
> + /* ISA extensions */
> + .cfg.mmu = true,
> + .cfg.vlenb = 256 >> 3,
> + .cfg.elen = 64,
> + .cfg.rvv_ma_all_1s = true,
> + .cfg.rvv_ta_all_1s = true,
> + .cfg.misa_w = true,
> + .cfg.pmp = true,
> + .cfg.cbom_blocksize = 64,
> + .cfg.cbop_blocksize = 64,
> + .cfg.cboz_blocksize = 64,
> + .cfg.ext_zic64b = true,
> + .cfg.ext_zicbom = true,
> + .cfg.ext_zicbop = true,
> + .cfg.ext_zicboz = true,
> + .cfg.ext_zicntr = true,
> + .cfg.ext_zicond = true,
> + .cfg.ext_zicsr = true,
> + .cfg.ext_zifencei = true,
> + .cfg.ext_zihintntl = true,
> + .cfg.ext_zihintpause = true,
> + .cfg.ext_zihpm = true,
> + .cfg.ext_zimop = true,
> + .cfg.ext_zawrs = true,
> + .cfg.ext_zfa = true,
> + .cfg.ext_zfbfmin = true,
> + .cfg.ext_zfh = true,
> + .cfg.ext_zfhmin = true,
> + .cfg.ext_zcb = true,
> + .cfg.ext_zcmop = true,
> + .cfg.ext_zba = true,
> + .cfg.ext_zbb = true,
> + .cfg.ext_zbs = true,
> + .cfg.ext_zkt = true,
> + .cfg.ext_zvbb = true,
> + .cfg.ext_zvbc = true,
> + .cfg.ext_zvfbfmin = true,
> + .cfg.ext_zvfbfwma = true,
> + .cfg.ext_zvfh = true,
> + .cfg.ext_zvfhmin = true,
> + .cfg.ext_zvkng = true,
> + .cfg.ext_smaia = true,
> + .cfg.ext_smstateen = true,
> + .cfg.ext_ssaia = true,
> + .cfg.ext_sscofpmf = true,
> + .cfg.ext_sstc = true,
> + .cfg.ext_svade = true,
> + .cfg.ext_svinval = true,
> + .cfg.ext_svnapot = true,
> + .cfg.ext_svpbmt = true,
> +
> + .cfg.max_satp_mode = VM_1_10_SV57,
> + ),
> +
> DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, MXL_RV64,
> rv64_veyron_v1_cpu_init),
> DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_XIANGSHAN_NANHU,
> MXL_RV64,
> rv64_xiangshan_nanhu_cpu_init),
> --
> 2.49.0
>
