[This is on top of v5 of the ID register storage rework: https://lore.kernel.org/qemu-devel/20250409144304.912325-1-coh...@redhat.com/T/#t]
It's been a while, but here's finally a respin of the series to make ID registers configurable directly via the command line. Major changes from v2 include: - split out the rework of ID register storage (see above) and rebased on top of that - hopefully improved the documentation - fixed some bugs along the way (including output of the cpu model expansion command, and compilation with HVF on) Decided against zeroing unknown registers; it's mostly a "dammed if you do, dammed if you don't" situation as one case or the other will not quite work as desired, even disregarding fields like AA64PFR1_EL1.MTE_frac where 0 might indicate things we do not support. You'll need to be careful when doing kernel updates and be explicit with configuring fields. The current cpu properties stay as they are; we can work on converting them to compatibility props once we have support for configuring the ID register fields on the command line for the other accelerators (this is still KVM only.) The FEAT_xxx features only support a subset of what we need to configure in real life; for example, different AltraMax machines differ in CTR_EL0, which is not covered by any FEAT_. It might make sense to provide them as syntactic sugar on top. We still have to deal with MIDR/REVIDR/AIDR differences by exploiting https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit?id=d300b0168ea8fd5022a1413bd37ab63f4e5a7d4d (in a different series.) I have not ignored the issue of named models on Arm, I just wanted to get the base infrastructure into place first :) Real world example (migration Graviton 3 -> 4, thx to Sebastian): -cpu host,pauth=off,SYSREG_ID_AA64PFR0_EL1_SEL2=0,SYSREG_ID_AA64PFR0_EL1_EL0=1, SYSREG_ID_AA64ISAR0_EL1_TLB=0,SYSREG_ID_AA64ISAR0_EL1_TS=0, SYSREG_ID_AA64ISAR0_EL1_SM4=0,SYSREG_ID_AA64ISAR0_EL1_SM3=0, SYSREG_ID_AA64ISAR1_EL1_SPECRES=0,SYSREG_ID_AA64ISAR1_EL1_SB=0, SYSREG_ID_AA64ISAR1_EL1_FRINTTS=0,SYSREG_ID_AA64MMFR0_EL1_TGRAN4_2=1, SYSREG_ID_AA64MMFR0_EL1_TGRAN16_2=1,SYSREG_ID_AA64MMFR0_EL1_TGRAN64_2=1 (not including handling MIDR differences, which is out of scope for this series) Code also available at https://gitlab.com/cohuck/qemu/-/tree/arm-cpu-model-rfcv3?ref_type=heads Cornelia Huck (5): arm/cpu: Add generated sysreg properties kvm: kvm_get_writable_id_regs arm/cpu: accessors for writable id registers arm-qmp-cmds: introspection for ID register props arm/cpu-features: document ID reg properties Eric Auger (5): arm/cpu: Add infra to handle generated ID register definitions arm/cpu: Add sysreg properties generation arm/kvm: Allow reading all the writable ID registers arm/kvm: write back modified ID regs to KVM arm/cpu: more customization for the kvm host cpu model docs/system/arm/cpu-features.rst | 104 +++- scripts/gen-cpu-sysreg-properties.awk | 325 ++++++++++++ scripts/update-aarch64-sysreg-code.sh | 5 +- target/arm/arm-qmp-cmds.c | 19 + target/arm/cpu-custom.h | 60 +++ target/arm/cpu-sysreg-properties.c | 713 ++++++++++++++++++++++++++ target/arm/cpu-sysregs.h | 2 + target/arm/cpu.c | 12 + target/arm/cpu.h | 47 ++ target/arm/cpu64.c | 24 +- target/arm/kvm.c | 289 ++++++++++- target/arm/kvm_arm.h | 26 +- target/arm/meson.build | 1 + target/arm/trace-events | 6 + 14 files changed, 1617 insertions(+), 16 deletions(-) create mode 100755 scripts/gen-cpu-sysreg-properties.awk create mode 100644 target/arm/cpu-custom.h create mode 100644 target/arm/cpu-sysreg-properties.c -- 2.49.0
