On Thu, Mar 13, 2025 at 1:57 AM Paolo Savini <paolo.sav...@embecosm.com> wrote: > > Previous version: > > - PATCH v1: > https://lore.kernel.org/all/20250211182056.412867-1-paolo.sav...@embecosm.com/ > > Follwing the suggestion in the following review by Daniel Barboza: > > https://lore.kernel.org/all/9be2ecc4-fed3-4774-a921-259f36e23...@ventanamicro.com/ > > we simplified the emulation by tcg nodes of such a complex operation as > strided > loads/stores by breaking it into two separate functions. > One function implements the loop that performs the main load/store operation > with the supporting logic to address the vector elements with the right stride > and to fill with ones the inactive elements in the case of a load. > The second function implements the loop that sets to 1 the tail bytes if we > are in a tail agnostic regime. > > Cc: Richard Handerson <richard.hender...@linaro.org> > Cc: Palmer Dabbelt <pal...@dabbelt.com> > Cc: Alistair Francis <alistair.fran...@wdc.com> > Cc: Bin Meng <bmeng...@gmail.com> > Cc: Weiwei Li <liwei1...@gmail.com> > Cc: Daniel Henrique Barboza <dbarb...@ventanamicro.com> > Cc: Liu Zhiwei <zhiwei_...@linux.alibaba.com> > Cc: Helene Chelin <helene.che...@embecosm.com> > Cc: Nathan Egge <ne...@google.com> > Cc: Max Chou <max.c...@sifive.com> > Cc: Jeremy Bennett <jeremy.benn...@embecosm.com> > Cc: Craig Blackmore <craig.blackm...@embecosm.com> > > > Paolo Savini (1): > [RISC-V/RVV] Generate strided vector loads/stores with tcg nodes.
Thanks! Applied to riscv-to-apply.next Alistair > > target/riscv/insn_trans/trans_rvv.c.inc | 323 ++++++++++++++++++++---- > 1 file changed, 273 insertions(+), 50 deletions(-) > > -- > 2.34.1 >
