Re: [PATCH RFC] target: riscv: Add Svrsw60b59b extension support

[Daniel Henrique Barboza]

On 3/14/25 9:11 AM, Alexandre Ghiti wrote:

On Fri, Mar 14, 2025 at 11:48 AM Alexandre Ghiti <alexgh...@rivosinc.com> wrote:

The Svrsw60b59b extension allows to free the PTE reserved bits 60 and 59
for software to use.

I missed that the extension had been renamed to Svrsw60*t*59b, I'll
fix that in v2 later after I collect some feedback.

Just to be clear: the extension is going to be named Svrsw60t59b, not
"Svrsw60*t*59b". Correct?


Aside from that code LGTM. Thanks,

Daniel

Thanks,

Alex

Signed-off-by: Alexandre Ghiti <alexgh...@rivosinc.com>
---

I tested it by always setting the bits 60 and 59 in Linux which booted
fine.

  target/riscv/cpu.c        | 2 ++
  target/riscv/cpu_bits.h   | 3 ++-
  target/riscv/cpu_cfg.h    | 1 +
  target/riscv/cpu_helper.c | 3 ++-
  4 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 3d4bd157d2..ee89cdef46 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -219,6 +219,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
      ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval),
      ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot),
      ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt),
+    ISA_EXT_DATA_ENTRY(svrsw60b59b, PRIV_VERSION_1_13_0, ext_svrsw60b59b),
      ISA_EXT_DATA_ENTRY(svukte, PRIV_VERSION_1_13_0, ext_svukte),
      ISA_EXT_DATA_ENTRY(svvptc, PRIV_VERSION_1_13_0, ext_svvptc),
      ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba),
@@ -1644,6 +1645,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
      MULTI_EXT_CFG_BOOL("svinval", ext_svinval, false),
      MULTI_EXT_CFG_BOOL("svnapot", ext_svnapot, false),
      MULTI_EXT_CFG_BOOL("svpbmt", ext_svpbmt, false),
+    MULTI_EXT_CFG_BOOL("svrsw60b59b", ext_svrsw60b59b, false),
      MULTI_EXT_CFG_BOOL("svvptc", ext_svvptc, true),

      MULTI_EXT_CFG_BOOL("zicntr", ext_zicntr, true),
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index f97c48a394..71f9e603c5 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -663,7 +663,8 @@ typedef enum {
  #define PTE_SOFT            0x300 /* Reserved for Software */
  #define PTE_PBMT            0x6000000000000000ULL /* Page-based memory types 
*/
  #define PTE_N               0x8000000000000000ULL /* NAPOT translation */
-#define PTE_RESERVED        0x1FC0000000000000ULL /* Reserved bits */
+#define PTE_RESERVED(svrsw60b59b)              \
+               (svrsw60b59b ? 0x07C0000000000000ULL : 0x1FC0000000000000ULL) 
/* Reserved bits */
  #define PTE_ATTR            (PTE_N | PTE_PBMT) /* All attributes bits */

  /* Page table PPN shift amount */
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index b410b1e603..f6e4b0068a 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -89,6 +89,7 @@ struct RISCVCPUConfig {
      bool ext_svinval;
      bool ext_svnapot;
      bool ext_svpbmt;
+    bool ext_svrsw60b59b;
      bool ext_svvptc;
      bool ext_svukte;
      bool ext_zdinx;
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index e1dfc4ecbf..6546cea403 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -1156,6 +1156,7 @@ static int get_physical_address(CPURISCVState *env, 
hwaddr *physical,
      bool svade = riscv_cpu_cfg(env)->ext_svade;
      bool svadu = riscv_cpu_cfg(env)->ext_svadu;
      bool adue = svadu ? env->menvcfg & MENVCFG_ADUE : !svade;
+    bool svrsw60b59b = riscv_cpu_cfg(env)->ext_svrsw60b59b;

      if (first_stage && two_stage && env->virt_enabled) {
          pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE);
@@ -1225,7 +1226,7 @@ restart:
          if (riscv_cpu_sxl(env) == MXL_RV32) {
              ppn = pte >> PTE_PPN_SHIFT;
          } else {
-            if (pte & PTE_RESERVED) {
+            if (pte & PTE_RESERVED(svrsw60b59b)) {
                  return TRANSLATE_FAIL;
              }

--
2.39.2