On Wed, Mar 05 2025, Richard Henderson <richard.hender...@linaro.org> wrote:
> On 3/5/25 08:38, Cornelia Huck wrote:
>> +++ b/target/arm/cpu-sysregs.h
>> @@ -0,0 +1,131 @@
>> +#ifndef ARM_CPU_SYSREGS_H
>> +#define ARM_CPU_SYSREGS_H
>> +
>> +/*
>> + * Following is similar to the coprocessor regs encodings, but with an
>> argument
>> + * ordering that matches the ARM ARM. We also reuse the various CP_REG_
>> defines
>> + * that actually are the same as the equivalent KVM_REG_ values.
>> + */
>> +#define ENCODE_ID_REG(op0, op1, crn, crm, op2) \
>> + (((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \
>> + ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \
>> + ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \
>> + ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \
>> + ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT))
>> +
>> +typedef enum ARMIDRegisterIdx {
>> + ID_AA64PFR0_EL1_IDX,
>> + ID_AA64PFR1_EL1_IDX,
>> + ID_AA64SMFR0_EL1_IDX,
>> + ID_AA64DFR0_EL1_IDX,
>> + ID_AA64DFR1_EL1_IDX,
>> + ID_AA64ISAR0_EL1_IDX,
>> + ID_AA64ISAR1_EL1_IDX,
>> + ID_AA64ISAR2_EL1_IDX,
>> + ID_AA64MMFR0_EL1_IDX,
>> + ID_AA64MMFR1_EL1_IDX,
>> + ID_AA64MMFR2_EL1_IDX,
>> + ID_AA64MMFR3_EL1_IDX,
>> + ID_PFR0_EL1_IDX,
>> + ID_PFR1_EL1_IDX,
>> + ID_DFR0_EL1_IDX,
>> + ID_MMFR0_EL1_IDX,
>> + ID_MMFR1_EL1_IDX,
>> + ID_MMFR2_EL1_IDX,
>> + ID_MMFR3_EL1_IDX,
>> + ID_ISAR0_EL1_IDX,
>> + ID_ISAR1_EL1_IDX,
>> + ID_ISAR2_EL1_IDX,
>> + ID_ISAR3_EL1_IDX,
>> + ID_ISAR4_EL1_IDX,
>> + ID_ISAR5_EL1_IDX,
>> + ID_MMFR4_EL1_IDX,
>> + ID_ISAR6_EL1_IDX,
>> + MVFR0_EL1_IDX,
>> + MVFR1_EL1_IDX,
>> + MVFR2_EL1_IDX,
>> + ID_PFR2_EL1_IDX,
>> + ID_DFR1_EL1_IDX,
>> + ID_MMFR5_EL1_IDX,
>> + ID_AA64ZFR0_EL1_IDX,
>> + CTR_EL0_IDX,
>> + NUM_ID_IDX,
>> +} ARMIDRegisterIdx;
>> +
>> +typedef enum ARMSysRegs {
>> + SYS_ID_AA64PFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 4, 0),
>> + SYS_ID_AA64PFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 4, 1),
>> + SYS_ID_AA64SMFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 4, 5),
>> + SYS_ID_AA64DFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 5, 0),
>> + SYS_ID_AA64DFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 5, 1),
>> + SYS_ID_AA64ISAR0_EL1 = ENCODE_ID_REG(3, 0, 0, 6, 0),
>> + SYS_ID_AA64ISAR1_EL1 = ENCODE_ID_REG(3, 0, 0, 6, 1),
>> + SYS_ID_AA64ISAR2_EL1 = ENCODE_ID_REG(3, 0, 0, 6, 2),
>> + SYS_ID_AA64MMFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 7, 0),
>> + SYS_ID_AA64MMFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 7, 1),
>> + SYS_ID_AA64MMFR2_EL1 = ENCODE_ID_REG(3, 0, 0, 7, 2),
>> + SYS_ID_AA64MMFR3_EL1 = ENCODE_ID_REG(3, 0, 0, 7, 3),
>> + SYS_ID_PFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 0),
>> + SYS_ID_PFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 1),
>> + SYS_ID_DFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 2),
>> + SYS_ID_MMFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 4),
>> + SYS_ID_MMFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 5),
>> + SYS_ID_MMFR2_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 6),
>> + SYS_ID_MMFR3_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 7),
>> + SYS_ID_ISAR0_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 0),
>> + SYS_ID_ISAR1_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 1),
>> + SYS_ID_ISAR2_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 2),
>> + SYS_ID_ISAR3_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 3),
>> + SYS_ID_ISAR4_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 4),
>> + SYS_ID_ISAR5_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 5),
>> + SYS_ID_MMFR4_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 6),
>> + SYS_ID_ISAR6_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 7),
>> + SYS_MVFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 3, 0),
>> + SYS_MVFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 3, 1),
>> + SYS_MVFR2_EL1 = ENCODE_ID_REG(3, 0, 0, 3, 2),
>> + SYS_ID_PFR2_EL1 = ENCODE_ID_REG(3, 0, 0, 3, 4),
>> + SYS_ID_DFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 3, 5),
>> + SYS_ID_MMFR5_EL1 = ENCODE_ID_REG(3, 0, 0, 3, 6),
>> + SYS_ID_AA64ZFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 4, 4),
>> + SYS_CTR_EL0 = ENCODE_ID_REG(3, 3, 0, 0, 1),
>> +} ARMSysRegs;
>> +
>> +static const uint32_t id_register_sysreg[NUM_ID_IDX] = {
>> + [ID_AA64PFR0_EL1_IDX] = SYS_ID_AA64PFR0_EL1,
>> + [ID_AA64PFR1_EL1_IDX] = SYS_ID_AA64PFR1_EL1,
>> + [ID_AA64SMFR0_EL1_IDX] = SYS_ID_AA64SMFR0_EL1,
>> + [ID_AA64DFR0_EL1_IDX] = SYS_ID_AA64DFR0_EL1,
>> + [ID_AA64DFR1_EL1_IDX] = SYS_ID_AA64DFR1_EL1,
>> + [ID_AA64ISAR0_EL1_IDX] = SYS_ID_AA64ISAR0_EL1,
>> + [ID_AA64ISAR1_EL1_IDX] = SYS_ID_AA64ISAR1_EL1,
>> + [ID_AA64ISAR2_EL1_IDX] = SYS_ID_AA64ISAR2_EL1,
>> + [ID_AA64MMFR0_EL1_IDX] = SYS_ID_AA64MMFR0_EL1,
>> + [ID_AA64MMFR1_EL1_IDX] = SYS_ID_AA64MMFR1_EL1,
>> + [ID_AA64MMFR2_EL1_IDX] = SYS_ID_AA64MMFR2_EL1,
>> + [ID_AA64MMFR3_EL1_IDX] = SYS_ID_AA64MMFR3_EL1,
>> + [ID_PFR0_EL1_IDX] = SYS_ID_PFR0_EL1,
>> + [ID_PFR1_EL1_IDX] = SYS_ID_PFR1_EL1,
>> + [ID_DFR0_EL1_IDX] = SYS_ID_DFR0_EL1,
>> + [ID_MMFR0_EL1_IDX] = SYS_ID_MMFR0_EL1,
>> + [ID_MMFR1_EL1_IDX] = SYS_ID_MMFR1_EL1,
>> + [ID_MMFR2_EL1_IDX] = SYS_ID_MMFR2_EL1,
>> + [ID_MMFR3_EL1_IDX] = SYS_ID_MMFR3_EL1,
>> + [ID_ISAR0_EL1_IDX] = SYS_ID_ISAR0_EL1,
>> + [ID_ISAR1_EL1_IDX] = SYS_ID_ISAR1_EL1,
>> + [ID_ISAR2_EL1_IDX] = SYS_ID_ISAR2_EL1,
>> + [ID_ISAR3_EL1_IDX] = SYS_ID_ISAR3_EL1,
>> + [ID_ISAR4_EL1_IDX] = SYS_ID_ISAR4_EL1,
>> + [ID_ISAR5_EL1_IDX] = SYS_ID_ISAR5_EL1,
>> + [ID_MMFR4_EL1_IDX] = SYS_ID_MMFR4_EL1,
>> + [ID_ISAR6_EL1_IDX] = SYS_ID_ISAR6_EL1,
>> + [MVFR0_EL1_IDX] = SYS_MVFR0_EL1,
>> + [MVFR1_EL1_IDX] = SYS_MVFR1_EL1,
>> + [MVFR2_EL1_IDX] = SYS_MVFR2_EL1,
>> + [ID_PFR2_EL1_IDX] = SYS_ID_PFR2_EL1,
>> + [ID_DFR1_EL1_IDX] = SYS_ID_DFR1_EL1,
>> + [ID_MMFR5_EL1_IDX] = SYS_ID_MMFR5_EL1,
>> + [ID_AA64ZFR0_EL1_IDX] = SYS_ID_AA64ZFR0_EL1,
>> + [CTR_EL0_IDX] = SYS_CTR_EL0,
>> +};
>
> Again, you should NOT place this array in a header,
> to be replicated in every single user of the header.
Hrm, I thought I had addressed this... but apparently not.
>
>
> This can be a bit more automated to avoid mistakes.
You mean to reduce this to a single invocation of the parsing script?
(The hand-written version is more error prone, I agree.)
>
> --- target/arm/cpu-sysregs.h.inc
>
> DEF(ID_AA64PFR0_EL1, 3, 0, 0, 4, 0)
> ...
>
> --- target/arm/cpu-sysregs.h
>
> #define DEF(NAME, OP0, OP1, CRN, CRM, OP2) NAME##_IDX,
>
> typedef enum ARMIDRegisterIdx {
> #include "cpu-sysregs.h.inc"
> } ARMIDRegisterIdx;
>
> #undef DEF
> #define DEF(NAME, OP0, OP1, CRN, CRM, OP2) \
> SYS_##NAME = ENCODE_ID_REG(OP0, OP1, CRN, CRM, OP2),
>
> typedef enum ARMSysRegs {
> #include "cpu-sysregs.h.inc"
> } ARMSysRegs;
>
> #undef DEF
>
>
> r~
