Hi Cedric,
> Subject: Re: [PATCH v4 19/23] hw/arm/aspeed: Add SoC and Machine Support
> for AST2700 A1
>
> On 3/3/25 10:54, Jamin Lin wrote:
> > The memory map for AST2700 A1 remains compatible with AST2700 A0.
> > However, the IRQ mapping has been updated for AST2700 A1, with GIC
> > interrupts now ranging from 192 to 201. Add a new IRQ map table for
> AST2700 A1.
> > Add "aspeed_soc_ast2700a1_class_init" to initialize the AST2700 A1 SoC.
> > Introduce "aspeed_machine_ast2700a1_evb_class_init" to initialize the
> > AST2700 A1 EVB.
>
> This could have been 2 patches. Minor.
>
Thanks for review and suggestion.
I will split 2 patches.
Jamin
> > Signed-off-by: Jamin Lin <jamin_...@aspeedtech.com>
>
> Reviewed-by: Cédric Le Goater <c...@redhat.com>
>
> Thanks,
>
> C.
>
>
> > ---
> > hw/arm/aspeed.c | 24 +++++++++++++
> > hw/arm/aspeed_ast27x0.c | 80
> +++++++++++++++++++++++++++++++++++++++++
> > 2 files changed, 104 insertions(+)
> >
> > diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index
> > 2482f05154..aaf63022ff 100644
> > --- a/hw/arm/aspeed.c
> > +++ b/hw/arm/aspeed.c
> > @@ -1693,6 +1693,26 @@ static void
> aspeed_machine_ast2700a0_evb_class_init(ObjectClass *oc, void *data)
> > mc->default_ram_size = 1 * GiB;
> > aspeed_machine_class_init_cpus_defaults(mc);
> > }
> > +
> > +static void aspeed_machine_ast2700a1_evb_class_init(ObjectClass *oc,
> > +void *data) {
> > + MachineClass *mc = MACHINE_CLASS(oc);
> > + AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
> > +
> > + mc->desc = "Aspeed AST2700 A1 EVB (Cortex-A35)";
> > + amc->soc_name = "ast2700-a1";
> > + amc->hw_strap1 = AST2700_EVB_HW_STRAP1;
> > + amc->hw_strap2 = AST2700_EVB_HW_STRAP2;
> > + amc->fmc_model = "w25q01jvq";
> > + amc->spi_model = "w25q512jv";
> > + amc->num_cs = 2;
> > + amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON |
> ASPEED_MAC2_ON;
> > + amc->uart_default = ASPEED_DEV_UART12;
> > + amc->i2c_init = ast2700_evb_i2c_init;
> > + mc->auto_create_sdcard = true;
> > + mc->default_ram_size = 1 * GiB;
> > + aspeed_machine_class_init_cpus_defaults(mc);
> > +}
> > #endif
> >
> > static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass
> > *oc, @@ -1821,6 +1841,10 @@ static const TypeInfo
> aspeed_machine_types[] = {
> > .name = MACHINE_TYPE_NAME("ast2700a0-evb"),
> > .parent = TYPE_ASPEED_MACHINE,
> > .class_init = aspeed_machine_ast2700a0_evb_class_init,
> > + }, {
> > + .name = MACHINE_TYPE_NAME("ast2700a1-evb"),
> > + .parent = TYPE_ASPEED_MACHINE,
> > + .class_init = aspeed_machine_ast2700a1_evb_class_init,
> > #endif
> > }, {
> > .name = TYPE_ASPEED_MACHINE,
> > diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index
> > 028bf08d0e..6d80b54470 100644
> > --- a/hw/arm/aspeed_ast27x0.c
> > +++ b/hw/arm/aspeed_ast27x0.c
> > @@ -120,6 +120,52 @@ static const int aspeed_soc_ast2700a0_irqmap[] = {
> > [ASPEED_DEV_SDHCI] = 133,
> > };
> >
> > +static const int aspeed_soc_ast2700a1_irqmap[] = {
> > + [ASPEED_DEV_SDMC] = 0,
> > + [ASPEED_DEV_HACE] = 4,
> > + [ASPEED_DEV_XDMA] = 5,
> > + [ASPEED_DEV_UART4] = 8,
> > + [ASPEED_DEV_SCU] = 12,
> > + [ASPEED_DEV_RTC] = 13,
> > + [ASPEED_DEV_EMMC] = 15,
> > + [ASPEED_DEV_TIMER1] = 16,
> > + [ASPEED_DEV_TIMER2] = 17,
> > + [ASPEED_DEV_TIMER3] = 18,
> > + [ASPEED_DEV_TIMER4] = 19,
> > + [ASPEED_DEV_TIMER5] = 20,
> > + [ASPEED_DEV_TIMER6] = 21,
> > + [ASPEED_DEV_TIMER7] = 22,
> > + [ASPEED_DEV_TIMER8] = 23,
> > + [ASPEED_DEV_DP] = 28,
> > + [ASPEED_DEV_LPC] = 192,
> > + [ASPEED_DEV_IBT] = 192,
> > + [ASPEED_DEV_KCS] = 192,
> > + [ASPEED_DEV_I2C] = 194,
> > + [ASPEED_DEV_ADC] = 194,
> > + [ASPEED_DEV_GPIO] = 194,
> > + [ASPEED_DEV_FMC] = 195,
> > + [ASPEED_DEV_WDT] = 195,
> > + [ASPEED_DEV_PWM] = 195,
> > + [ASPEED_DEV_I3C] = 195,
> > + [ASPEED_DEV_UART0] = 196,
> > + [ASPEED_DEV_UART1] = 196,
> > + [ASPEED_DEV_UART2] = 196,
> > + [ASPEED_DEV_UART3] = 196,
> > + [ASPEED_DEV_UART5] = 196,
> > + [ASPEED_DEV_UART6] = 196,
> > + [ASPEED_DEV_UART7] = 196,
> > + [ASPEED_DEV_UART8] = 196,
> > + [ASPEED_DEV_UART9] = 196,
> > + [ASPEED_DEV_UART10] = 196,
> > + [ASPEED_DEV_UART11] = 196,
> > + [ASPEED_DEV_UART12] = 196,
> > + [ASPEED_DEV_ETH1] = 196,
> > + [ASPEED_DEV_ETH2] = 196,
> > + [ASPEED_DEV_ETH3] = 196,
> > + [ASPEED_DEV_PECI] = 197,
> > + [ASPEED_DEV_SDHCI] = 197,
> > +};
> > +
> > /* GICINT 128 */
> > /* GICINT 192 */
> > static const int ast2700_gic128_gic192_intcmap[] = { @@ -860,6
> > +906,34 @@ static void aspeed_soc_ast2700a0_class_init(ObjectClass *oc,
> void *data)
> > sc->get_irq = aspeed_soc_ast2700_get_irq;
> > }
> >
> > +static void aspeed_soc_ast2700a1_class_init(ObjectClass *oc, void
> > +*data) {
> > + static const char * const valid_cpu_types[] = {
> > + ARM_CPU_TYPE_NAME("cortex-a35"),
> > + NULL
> > + };
> > + DeviceClass *dc = DEVICE_CLASS(oc);
> > + AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
> > +
> > + /* Reason: The Aspeed SoC can only be instantiated from a board */
> > + dc->user_creatable = false;
> > + dc->realize = aspeed_soc_ast2700_realize;
> > +
> > + sc->name = "ast2700-a1";
> > + sc->valid_cpu_types = valid_cpu_types;
> > + sc->silicon_rev = AST2700_A1_SILICON_REV;
> > + sc->sram_size = 0x20000;
> > + sc->spis_num = 3;
> > + sc->wdts_num = 8;
> > + sc->macs_num = 3;
> > + sc->uarts_num = 13;
> > + sc->num_cpus = 4;
> > + sc->uarts_base = ASPEED_DEV_UART0;
> > + sc->irqmap = aspeed_soc_ast2700a1_irqmap;
> > + sc->memmap = aspeed_soc_ast2700_memmap;
> > + sc->get_irq = aspeed_soc_ast2700_get_irq;
> > +}
> > +
> > static const TypeInfo aspeed_soc_ast27x0_types[] = {
> > {
> > .name = TYPE_ASPEED27X0_SOC,
> > @@ -872,6 +946,12 @@ static const TypeInfo aspeed_soc_ast27x0_types[] =
> {
> > .instance_init = aspeed_soc_ast2700_init,
> > .class_init = aspeed_soc_ast2700a0_class_init,
> > },
> > + {
> > + .name = "ast2700-a1",
> > + .parent = TYPE_ASPEED27X0_SOC,
> > + .instance_init = aspeed_soc_ast2700_init,
> > + .class_init = aspeed_soc_ast2700a1_class_init,
> > + },
> > };
> >
> > DEFINE_TYPES(aspeed_soc_ast27x0_types)
