On 2025/2/25 上午8:40, Jiaxun Yang wrote:
Hi all,
This series is a collection of small fixes I made to TCG for
LoongArch32.
There are still many thing broken, especially on CSRs. More
series following. However this is sufficient to boot 32bit
kernel.
Is there any product introduction about LoongArch32 board? such as MMU
type, memory type(DDR or SRAM), interrupt controller type.
Regards
Bibo Mao
Thanks for revivewing!
Signed-off-by: Jiaxun Yang <jiaxun.y...@flygoat.com>
---
Changes in v2:
- Addressing minor review comments
- Don't create 32bit vairant, simply allow 32bit CPU on qemu-loongarch64
- Link to v1:
https://lore.kernel.org/r/20241222-la32-fixes1-v1-0-8c62b7e59...@flygoat.com
---
Jiaxun Yang (9):
target/loongarch: Enable rotr.w/rotri.w for LoongArch32
target/loongarch: Fix address generation for gen_sc
target/loongarch: Fix PGD CSR for LoongArch32
target/loongarch: Perform sign extension for IOCSR reads
target/loongarch: Use target_ulong for iocsrrd helper results
target/loongarch: Fix some modifiers for log formatting
target/loongarch: Use target_ulong for CSR helpers
target/loongarch: Fix load type for gen_ll
target/loongarch: Introduce max32 CPU type
target/loongarch/cpu.c | 152 +++++++++++++++++----
target/loongarch/helper.h | 22 +--
target/loongarch/tcg/csr_helper.c | 2 +-
target/loongarch/tcg/insn_trans/trans_atomic.c.inc | 8 +-
target/loongarch/tcg/insn_trans/trans_shift.c.inc | 4 +-
target/loongarch/tcg/iocsr_helper.c | 20 +--
target/loongarch/tcg/op_helper.c | 4 +-
target/loongarch/tcg/tlb_helper.c | 2 +-
target/loongarch/tcg/translate.c | 5 +-
9 files changed, 155 insertions(+), 64 deletions(-)
---
base-commit: 65cb7129f4160c7e07a0da107f888ec73ae96776
change-id: 20241222-la32-fixes1-368cc14d0986
Best regards,
