On Mon, 30 Apr 2012, Alexander Graf wrote:
>
> On 30.04.2012, at 12:45, Alexander Graf wrote:
>
> >
> > On 22.04.2012, at 15:26, Blue Swirl wrote:
> >
> >> Add an explicit CPUPPCState parameter instead of relying on AREG0
> >> and rename op_helper.c (which only contains load and store helpers)
> >> to mem_helper.c. Remove AREG0 swapping in
> >> tlb_fill().
> >>
> >> Switch to AREG0 free mode. Use cpu_ld{l,uw}_code in translation
> >> and interrupt handling, cpu_{ld,st}{l,uw}_data in loads and stores.
> >
> > This patch breaks qemu-system-ppc64 on ppc32 host user space for me. I'm
> > trying to debug it down, but worst case I'll omit this patch set for 1.1.
>
> Ok, so apparently nobody ever tested TCG_AREG0 mode with the ppc tcg
> target. It looks as if the
> 64-bit-guest-registers-in-32-bit-host-registers code path is missing
> completely.
>
> This actually makes me less confident that this is a change we want for
> 1.1. I'll remove the patches from the queue.
>
>
> Alex
>
>
> TCG register swizzling code:
>
> #ifdef CONFIG_TCG_PASS_AREG0
> /* XXX/FIXME: suboptimal */
> tcg_out_mov(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[3],
> tcg_target_call_iarg_regs[2]);
> tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[2],
> tcg_target_call_iarg_regs[1]);
> tcg_out_mov(s, TCG_TYPE_TL, tcg_target_call_iarg_regs[1],
> tcg_target_call_iarg_regs[0]);
> tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0],
> TCG_AREG0);
> #endif
> tcg_out_call (s, (tcg_target_long) qemu_st_helpers[opc], 1);
>
The above snippet is incorrect for SysV ppc32 ABI, due to misalignment
of long long argument in register file.
[..snip..]
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