On 2/7/25 7:46 PM, Richard Henderson wrote: > On 2/7/25 03:02, Cornelia Huck wrote: >> - t = cpu->isar.id_aa64zfr0; >> + t = GET_IDREG(idregs, ID_AA64ZFR0); >> t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1); >> t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* >> FEAT_SVE_PMULL128 */ >> t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); /* >> FEAT_SVE_BitPerm */ >> @@ -1252,7 +1262,7 @@ void aarch64_max_tcg_initfn(Object *obj) >> t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); /* FEAT_I8MM */ >> t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); /* FEAT_F32MM */ >> t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); /* FEAT_F64MM */ >> - cpu->isar.id_aa64zfr0 = t; >> + SET_IDREG(idregs, ID_AA64ZFR0, t); > > This doesn't belong to this patch. Yes my fault, ID_AA64ZFR0 handling can easily be put in a separate patch Eric > > > r~ >
