On Thu, Feb 6, 2025 at 7:59 PM Atish Patra <ati...@rivosinc.com> wrote:
>
> As per the latest privilege specification v1.13[1], the sscofpmf
> only reserves first 8 bits of hpmeventX. Update the corresponding
> masks accordingly.
>
> [1]https://github.com/riscv/riscv-isa-manual/issues/1578
>
> Reviewed-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
> Signed-off-by: Atish Patra <ati...@rivosinc.com>
Acked-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> target/riscv/cpu_bits.h | 5 ++---
> 1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index f97c48a3943f..74859c4bc8ff 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -933,9 +933,8 @@ typedef enum RISCVException {
> MHPMEVENTH_BIT_VSINH | \
> MHPMEVENTH_BIT_VUINH)
>
> -#define MHPMEVENT_SSCOF_MASK _ULL(0xFFFF000000000000)
> -#define MHPMEVENT_IDX_MASK 0xFFFFF
> -#define MHPMEVENT_SSCOF_RESVD 16
> +#define MHPMEVENT_SSCOF_MASK MAKE_64BIT_MASK(63, 56)
> +#define MHPMEVENT_IDX_MASK (~MHPMEVENT_SSCOF_MASK)
>
> /* RISC-V-specific interrupt pending bits. */
> #define CPU_INTERRUPT_RNMI CPU_INTERRUPT_TGT_EXT_0
>
> --
> 2.43.0
>
>
