> > Note that there is a 'guest-phys-bits' property for x86 CPUs, which is a > > hint for the guest what the usable address width is. It was added > > because there are cases where the guest simply can't figure that it is > > not possible to use the full physical address space of the cpu. There > > are some non-obvious limitations around 5-level paging. Intel has some > > CPUs with phys-bits > 48 but only 4-level EPT for example. > > > > So one option to handle this is to make sure guest-phys-bits is not > > larger than the iommu width. > > Yes. This is what I am trying to do. > > Patch [1] returns X86_CPU(cs)->phys_bits. I was not sure which *phys* > property to use. If you think this is incorrect and not returning the > right information, I will change the proposal with guest-phys-bits.
> [1] > https://lore.kernel.org/qemu-devel/20250130134346.1754143-8-...@redhat.com/ Yes, guest-phys-bits should be used here (and the helpers renamed too for consistency, to avoid making all this more complex than it already is). take care, Gerd
