Hi Joel, > From: Joel Stanley <j...@jms.id.au> > Sent: Thursday, February 6, 2025 12:55 PM > To: Jamin Lin <jamin_...@aspeedtech.com> > Cc: Andrew Jeffery <and...@codeconstruct.com.au>; Cédric Le Goater > <c...@kaod.org>; Peter Maydell <peter.mayd...@linaro.org>; Steven Lee > <steven_...@aspeedtech.com>; Troy Lee <leet...@gmail.com>; open > list:ASPEED BMCs <qemu-...@nongnu.org>; open list:All patches CC here > <qemu-devel@nongnu.org>; Troy Lee <troy_...@aspeedtech.com>; Yunlin > Tang <yunlin.t...@aspeedtech.com> > Subject: Re: [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two levels of > INTC controllers for AST2700 A1 > > Hi Jamin, > > On Thu, 6 Feb 2025 at 10:09, Andrew Jeffery <and...@codeconstruct.com.au> > wrote: > > Thanks, I'll consider this updated diagram as well while I put my own > > together from the other pieces of info you've provided. > > When you send the next version, please try to separate your code cleanups and > minor renames into a different patch. It makes it easier to see what you're > adding. > > Thanks, > > Joel
Thanks for suggestion. Cedric, also made the same suggestion in patch 0, https://patchwork.kernel.org/project/qemu-devel/cover/20250121070424.2465942-1-jamin_...@aspeedtech.com/ I think I will re-send this first. 1. INTC rename/prereqs/cleanups hw/intc/aspeed: Rename INTC to INTC0 hw/intc/aspeed: Support different memory region ops hw/intc/aspeed: Introduce a new aspeed_2700_intc0_ops for INTC0 hw/intc/aspeed: Support setting different memory and register size hw/intc/aspeed: Introduce helper functions for enable and status registers hw/intc/aspeed: Add ID to trace events for better debugging hw/arm/aspeed: Rename IRQ table and machine name for AST2700 A0 Jamin
