Thank you Richard for noticing the issue.
I have been able to create tests that show the malfunction of the FsTOx
instruction as well. I am however not yet able to prove(through tests) the
malfunction of the FxTO{s,d,q} instructions.
Based on the fact that the source registers are 64 bit, a similar pattern
should be used.
I also noticed a mistake I made in the patch with the FqTOx instruction, using
q_q2, instead of d_q2(since the destination registers are 64 bits).
I will resubmit this patch with corrections once I have managed to write tests
which show the issues.
Best regards
Mikael Szreder
On February 3, 2025 3:01:30 PM GMT+01:00, Mikael Szreder <g...@miszr.win> wrote:
>A bug was introduced in commit 0bba7572d40d which causes the fdtox and
> fqtox instructions to incorrectly select the destination registers.
>More information and a test program can be found in issue #2802.
>
>Fixes: 0bba7572d40d ("target/sparc: Perform DFPREG/QFPREG in decodetree")
>Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2802
>Signed-off-by: Mikael Szreder <g...@miszr.win>
>---
> target/sparc/insns.decode | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
>diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
>index 989c20b44a..694a28d88c 100644
>--- a/target/sparc/insns.decode
>+++ b/target/sparc/insns.decode
>@@ -322,8 +322,8 @@ FNHADDs 10 ..... 110100 ..... 0 0111 0001 .....
>@r_r_r
> FNHADDd 10 ..... 110100 ..... 0 0111 0010 ..... @d_d_d
> FNsMULd 10 ..... 110100 ..... 0 0111 1001 ..... @d_r_r
> FsTOx 10 ..... 110100 00000 0 1000 0001 ..... @r_r2
>-FdTOx 10 ..... 110100 00000 0 1000 0010 ..... @r_d2
>-FqTOx 10 ..... 110100 00000 0 1000 0011 ..... @r_q2
>+FdTOx 10 ..... 110100 00000 0 1000 0010 ..... @d_d2
>+FqTOx 10 ..... 110100 00000 0 1000 0011 ..... @q_q2
> FxTOs 10 ..... 110100 00000 0 1000 0100 ..... @r_r2
> FxTOd 10 ..... 110100 00000 0 1000 1000 ..... @d_r2
> FxTOq 10 ..... 110100 00000 0 1000 1100 ..... @q_r2
>--
>2.48.1
>
Git
