On Wed, 29 Jan 2025 at 01:39, Richard Henderson
<richard.hender...@linaro.org> wrote:
>
> Split negation cases out of gvec_fmla, creating 6 new helpers.
> We no longer pass 'neg' as a bit in simd_data.
>
> Handle FPCR.AH=0 via xor and FPCR.AH=1 via muladd flags.
> static bool do_fmla_vector_idx(DisasContext *s, arg_qrrx_e *a, bool neg)
> {
> - static gen_helper_gvec_4_ptr * const fns[3] = {
> - gen_helper_gvec_fmla_idx_h,
> - gen_helper_gvec_fmla_idx_s,
> - gen_helper_gvec_fmla_idx_d,
> + static gen_helper_gvec_4_ptr * const fns[3][3] = {
> + { gen_helper_gvec_fmla_idx_h,
> + gen_helper_gvec_fmla_idx_s,
> + gen_helper_gvec_fmla_idx_d },
> + { gen_helper_gvec_fmls_idx_h,
> + gen_helper_gvec_fmls_idx_s,
> + gen_helper_gvec_fmls_idx_d },
> + { gen_helper_gvec_ah_fmls_idx_h,
> + gen_helper_gvec_ah_fmls_idx_s,
> + gen_helper_gvec_ah_fmls_idx_d },
> };
> MemOp esz = a->esz;
> int check = fp_access_check_vector_hsd(s, a->q, esz);
> @@ -6756,8 +6762,7 @@ static bool do_fmla_vector_idx(DisasContext *s,
> arg_qrrx_e *a, bool neg)
>
> gen_gvec_op4_fpst(s, a->q, a->rd, a->rn, a->rm, a->rd,
> esz == MO_16 ? FPST_A64_F16 : FPST_A64,
> - (s->fpcr_ah << 5) | (a->idx << 1) | neg,
> - fns[esz - 1]);
> + a->idx, fns[esz - 1][neg ? 1 + s->fpcr_ah : 0]);
The indexes into fns[][] here are the wrong way around, so
if you try to do a FMLA on a double it hands you back
gen_helper_gvec_ah_fmls_idx_h ...
thanks
-- PMM
