Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
---
target/arm/tcg/translate.h | 14 +++++++-------
target/arm/tcg/translate-a64.c | 8 ++++----
target/arm/tcg/translate-sve.c | 8 ++++----
3 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h
index cc753419ed..d4ae39c469 100644
--- a/target/arm/tcg/translate.h
+++ b/target/arm/tcg/translate.h
@@ -678,8 +678,8 @@ typedef enum ARMFPStatusFlavour {
FPST_A64,
FPST_A32_F16,
FPST_A64_F16,
- FPST_FPCR_AH,
- FPST_FPCR_AH_F16,
+ FPST_AH,
+ FPST_AH_F16,
FPST_STD,
FPST_STD_F16,
} ARMFPStatusFlavour;
@@ -700,11 +700,11 @@ typedef enum ARMFPStatusFlavour {
* for AArch32 operations controlled by the FPCR where FPCR.FZ16 is to be
used
* FPST_A64_F16
* for AArch64 operations controlled by the FPCR where FPCR.FZ16 is to be
used
- * FPST_FPCR_AH:
+ * FPST_AH:
* for AArch64 operations which change behaviour when AH=1 (specifically,
* bfloat16 conversions and multiplies, and the reciprocal and square root
* estimate/step insns)
- * FPST_FPCR_AH_F16:
+ * FPST_AH_F16:
* ditto, but for half-precision operations
* FPST_STD
* for A32/T32 Neon operations using the "standard FPSCR value"
@@ -729,10 +729,10 @@ static inline TCGv_ptr fpstatus_ptr(ARMFPStatusFlavour
flavour)
case FPST_A64_F16:
offset = offsetof(CPUARMState, vfp.fp_status_f16_a64);
break;
- case FPST_FPCR_AH:
+ case FPST_AH:
offset = offsetof(CPUARMState, vfp.ah_fp_status);
break;
- case FPST_FPCR_AH_F16:
+ case FPST_AH_F16:
offset = offsetof(CPUARMState, vfp.ah_fp_status_f16);
break;
case FPST_STD:
@@ -755,7 +755,7 @@ static inline TCGv_ptr fpstatus_ptr(ARMFPStatusFlavour
flavour)
static inline ARMFPStatusFlavour select_fpst(DisasContext *s, MemOp esz)
{
if (s->fpcr_ah) {
- return esz == MO_16 ? FPST_FPCR_AH_F16 : FPST_FPCR_AH;
+ return esz == MO_16 ? FPST_AH_F16 : FPST_AH;
} else {
return esz == MO_16 ? FPST_A64_F16 : FPST_A64;
}
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 35d409685c..715760a17b 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -6135,7 +6135,7 @@ static bool trans_BFMLAL_v(DisasContext *s, arg_qrrr_e *a)
if (fp_access_check(s)) {
/* Q bit selects BFMLALB vs BFMLALT. */
gen_gvec_op4_fpst(s, true, a->rd, a->rn, a->rm, a->rd,
- s->fpcr_ah ? FPST_FPCR_AH : FPST_A64, a->q,
+ s->fpcr_ah ? FPST_AH : FPST_A64, a->q,
gen_helper_gvec_bfmlal);
}
return true;
@@ -6892,7 +6892,7 @@ static bool trans_BFMLAL_vi(DisasContext *s, arg_qrrx_e
*a)
if (fp_access_check(s)) {
/* Q bit selects BFMLALB vs BFMLALT. */
gen_gvec_op4_fpst(s, true, a->rd, a->rn, a->rm, a->rd,
- s->fpcr_ah ? FPST_FPCR_AH : FPST_A64,
+ s->fpcr_ah ? FPST_AH : FPST_A64,
(a->idx << 1) | a->q,
gen_helper_gvec_bfmlal_idx);
}
@@ -8866,7 +8866,7 @@ TRANS(FRINTX_s, do_fp1_scalar, a, &f_scalar_frintx, -1)
static bool trans_BFCVT_s(DisasContext *s, arg_rr_e *a)
{
- ARMFPStatusFlavour fpsttype = s->fpcr_ah ? FPST_FPCR_AH : FPST_A64;
+ ARMFPStatusFlavour fpsttype = s->fpcr_ah ? FPST_AH : FPST_A64;
TCGv_i32 t32;
int check;
@@ -9691,7 +9691,7 @@ static void gen_bfcvtn_hs(TCGv_i64 d, TCGv_i64 n)
static void gen_bfcvtn_ah_hs(TCGv_i64 d, TCGv_i64 n)
{
- TCGv_ptr fpst = fpstatus_ptr(FPST_FPCR_AH);
+ TCGv_ptr fpst = fpstatus_ptr(FPST_AH);
TCGv_i32 tmp = tcg_temp_new_i32();
gen_helper_bfcvt_pair(tmp, n, fpst);
tcg_gen_extu_i32_i64(d, tmp);
diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
index 3811316a2d..cb6bb27622 100644
--- a/target/arm/tcg/translate-sve.c
+++ b/target/arm/tcg/translate-sve.c
@@ -3985,7 +3985,7 @@ TRANS_FEAT(FCVT_hs, aa64_sve, gen_gvec_fpst_arg_zpz,
TRANS_FEAT(BFCVT, aa64_sve_bf16, gen_gvec_fpst_arg_zpz,
gen_helper_sve_bfcvt, a, 0,
- s->fpcr_ah ? FPST_FPCR_AH : FPST_A64)
+ s->fpcr_ah ? FPST_AH : FPST_A64)
TRANS_FEAT(FCVT_dh, aa64_sve, gen_gvec_fpst_arg_zpz,
gen_helper_sve_fcvt_dh, a, 0, FPST_A64)
@@ -7136,7 +7136,7 @@ TRANS_FEAT(FCVTNT_ds, aa64_sve2, gen_gvec_fpst_arg_zpz,
TRANS_FEAT(BFCVTNT, aa64_sve_bf16, gen_gvec_fpst_arg_zpz,
gen_helper_sve_bfcvtnt, a, 0,
- s->fpcr_ah ? FPST_FPCR_AH : FPST_A64)
+ s->fpcr_ah ? FPST_AH : FPST_A64)
TRANS_FEAT(FCVTLT_hs, aa64_sve2, gen_gvec_fpst_arg_zpz,
gen_helper_sve2_fcvtlt_hs, a, 0, FPST_A64)
@@ -7198,7 +7198,7 @@ static bool do_BFMLAL_zzzw(DisasContext *s, arg_rrrr_esz
*a, bool sel)
{
return gen_gvec_fpst_zzzz(s, gen_helper_gvec_bfmlal,
a->rd, a->rn, a->rm, a->ra, sel,
- s->fpcr_ah ? FPST_FPCR_AH : FPST_A64);
+ s->fpcr_ah ? FPST_AH : FPST_A64);
}
TRANS_FEAT(BFMLALB_zzzw, aa64_sve_bf16, do_BFMLAL_zzzw, a, false)
@@ -7209,7 +7209,7 @@ static bool do_BFMLAL_zzxw(DisasContext *s, arg_rrxr_esz
*a, bool sel)
return gen_gvec_fpst_zzzz(s, gen_helper_gvec_bfmlal_idx,
a->rd, a->rn, a->rm, a->ra,
(a->index << 1) | sel,
- s->fpcr_ah ? FPST_FPCR_AH : FPST_A64);
+ s->fpcr_ah ? FPST_AH : FPST_A64);
}
TRANS_FEAT(BFMLALB_zzxw, aa64_sve_bf16, do_BFMLAL_zzxw, a, false)
--
2.43.0
