Have the CPUClass::disas_set_info() callback set the disassemble_info::endian field.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org> --- target/riscv/cpu.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3d4bd157d2c..b39a701d751 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1156,6 +1156,15 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) CPURISCVState *env = &cpu->env; info->target_info = &cpu->cfg; + /* + * A couple of bits in MSTATUS set the endianness: + * - MSTATUS_UBE (User-mode), + * - MSTATUS_SBE (Supervisor-mode), + * - MSTATUS_MBE (Machine-mode) + * but we don't implement that yet. + */ + info->endian = BFD_ENDIAN_LITTLE; + switch (env->xl) { case MXL_RV32: info->print_insn = print_insn_riscv32; -- 2.47.1