Add logic cpu index input parameter for function cpu_by_arch_id,
CPUState::cpu_index is logic cpu slot index for possible_cpus.
At the same time it is logic index with LoongsonIPICommonState::IPICore,
here hide access for CPUState::cpu_index directly, it comes from
function cpu_by_arch_id().
Signed-off-by: Bibo Mao <maob...@loongson.cn>
Reviewed-by: Bibo Mao <maob...@loongson.cn>
---
hw/intc/loongarch_ipi.c | 19 +++++++++++++++----
hw/intc/loongson_ipi.c | 23 ++++++++++++++++++++++-
hw/intc/loongson_ipi_common.c | 21 ++++++++++++---------
include/hw/intc/loongson_ipi_common.h | 3 ++-
4 files changed, 51 insertions(+), 15 deletions(-)
diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c
index 41d9625dcb..515549e8a5 100644
--- a/hw/intc/loongarch_ipi.c
+++ b/hw/intc/loongarch_ipi.c
@@ -38,17 +38,28 @@ static CPUArchId *find_cpu_by_archid(MachineState *ms,
uint32_t id)
return found_cpu;
}
-static CPUState *loongarch_cpu_by_arch_id(int64_t arch_id)
+static int loongarch_cpu_by_arch_id(LoongsonIPICommonState *lics,
+ int64_t arch_id, int *index, CPUState
**pcs)
{
MachineState *machine = MACHINE(qdev_get_machine());
CPUArchId *archid;
+ CPUState *cs;
archid = find_cpu_by_archid(machine, arch_id);
- if (archid) {
- return CPU(archid->cpu);
+ if (archid && archid->cpu) {
+ cs = archid->cpu;
+ if (index) {
+ *index = cs->cpu_index;
+ }
+
+ if (pcs) {
+ *pcs = cs;
+ }
+
+ return MEMTX_OK;
}
- return NULL;
+ return MEMTX_ERROR;
}
static void loongarch_ipi_realize(DeviceState *dev, Error **errp)
diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
index 29e92d48fd..d2268a27f8 100644
--- a/hw/intc/loongson_ipi.c
+++ b/hw/intc/loongson_ipi.c
@@ -20,6 +20,27 @@ static AddressSpace *get_iocsr_as(CPUState *cpu)
return NULL;
}
+static int loongson_cpu_by_arch_id(LoongsonIPICommonState *lics,
+ int64_t arch_id, int *index, CPUState **pcs)
+{
+ CPUState *cs;
+
+ cs = cpu_by_arch_id(arch_id);
+ if (cs == NULL) {
+ return MEMTX_ERROR;
+ }
+
+ if (index) {
+ *index = cs->cpu_index;
+ }
+
+ if (pcs) {
+ *pcs = cs;
+ }
+
+ return MEMTX_OK;
+}
+
static const MemoryRegionOps loongson_ipi_core_ops = {
.read_with_attrs = loongson_ipi_core_readl,
.write_with_attrs = loongson_ipi_core_writel,
@@ -92,7 +113,7 @@ static void loongson_ipi_class_init(ObjectClass *klass, void
*data)
&lic->parent_unrealize);
device_class_set_props(dc, loongson_ipi_properties);
licc->get_iocsr_as = get_iocsr_as;
- licc->cpu_by_arch_id = cpu_by_arch_id;
+ licc->cpu_by_arch_id = loongson_cpu_by_arch_id;
}
static const TypeInfo loongson_ipi_types[] = {
diff --git a/hw/intc/loongson_ipi_common.c b/hw/intc/loongson_ipi_common.c
index 363cddc54c..f5ab5024c0 100644
--- a/hw/intc/loongson_ipi_common.c
+++ b/hw/intc/loongson_ipi_common.c
@@ -103,16 +103,17 @@ static MemTxResult mail_send(LoongsonIPICommonState *ipi,
uint32_t cpuid;
hwaddr addr;
CPUState *cs;
+ int cpu, ret;
cpuid = extract32(val, 16, 10);
- cs = licc->cpu_by_arch_id(cpuid);
- if (cs == NULL) {
+ ret = licc->cpu_by_arch_id(ipi, cpuid, &cpu, &cs);
+ if (ret != MEMTX_OK) {
return MEMTX_DECODE_ERROR;
}
/* override requester_id */
addr = SMP_IPI_MAILBOX + CORE_BUF_20 + (val & 0x1c);
- attrs.requester_id = cs->cpu_index;
+ attrs.requester_id = cpu;
return send_ipi_data(ipi, cs, val, addr, attrs);
}
@@ -123,16 +124,17 @@ static MemTxResult any_send(LoongsonIPICommonState *ipi,
uint32_t cpuid;
hwaddr addr;
CPUState *cs;
+ int cpu, ret;
cpuid = extract32(val, 16, 10);
- cs = licc->cpu_by_arch_id(cpuid);
- if (cs == NULL) {
+ ret = licc->cpu_by_arch_id(ipi, cpuid, &cpu, &cs);
+ if (ret != MEMTX_OK) {
return MEMTX_DECODE_ERROR;
}
/* override requester_id */
addr = val & 0xffff;
- attrs.requester_id = cs->cpu_index;
+ attrs.requester_id = cpu;
return send_ipi_data(ipi, cs, val, addr, attrs);
}
@@ -146,6 +148,7 @@ MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr
addr, uint64_t val,
uint32_t cpuid;
uint8_t vector;
CPUState *cs;
+ int cpu, ret;
addr &= 0xff;
trace_loongson_ipi_write(size, (uint64_t)addr, val);
@@ -176,11 +179,11 @@ MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr
addr, uint64_t val,
cpuid = extract32(val, 16, 10);
/* IPI status vector */
vector = extract8(val, 0, 5);
- cs = licc->cpu_by_arch_id(cpuid);
- if (cs == NULL || cs->cpu_index >= ipi->num_cpu) {
+ ret = licc->cpu_by_arch_id(ipi, cpuid, &cpu, &cs);
+ if (ret != MEMTX_OK || cpu >= ipi->num_cpu) {
return MEMTX_DECODE_ERROR;
}
- loongson_ipi_core_writel(&ipi->cpu[cs->cpu_index], CORE_SET_OFF,
+ loongson_ipi_core_writel(&ipi->cpu[cpu], CORE_SET_OFF,
BIT(vector), 4, attrs);
break;
default:
diff --git a/include/hw/intc/loongson_ipi_common.h
b/include/hw/intc/loongson_ipi_common.h
index 4192f3d548..b587f9c571 100644
--- a/include/hw/intc/loongson_ipi_common.h
+++ b/include/hw/intc/loongson_ipi_common.h
@@ -46,7 +46,8 @@ struct LoongsonIPICommonClass {
DeviceRealize parent_realize;
DeviceUnrealize parent_unrealize;
AddressSpace *(*get_iocsr_as)(CPUState *cpu);
- CPUState *(*cpu_by_arch_id)(int64_t id);
+ int (*cpu_by_arch_id)(LoongsonIPICommonState *lics, int64_t id,
+ int *index, CPUState **pcs);
};
MemTxResult loongson_ipi_core_readl(void *opaque, hwaddr addr, uint64_t *data,
--
2.43.5
