The e1000e and igb tests do not clear the ICR/EICR cause bits (or
set auto-clear) on seeing queue interrupts, which inhibits the
triggering of a new interrupt.
Fix this by clearing the cause bits, and verify that the expected
cause bit was set.
Cc: Michael S. Tsirkin <m...@redhat.com>
Cc: Marcel Apfelbaum <marcel.apfelb...@gmail.com>
Cc: Dmitry Fleytman <dmitry.fleyt...@gmail.com>
Cc: Akihiko Odaki <akihiko.od...@daynix.com>
Cc: Sriram Yagnaraman <sriram.yagnara...@ericsson.com>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
---
tests/qtest/e1000e-test.c | 4 ++++
tests/qtest/igb-test.c | 4 ++++
2 files changed, 8 insertions(+)
diff --git a/tests/qtest/e1000e-test.c b/tests/qtest/e1000e-test.c
index de9738fdb74..35548d1c20b 100644
--- a/tests/qtest/e1000e-test.c
+++ b/tests/qtest/e1000e-test.c
@@ -66,6 +66,8 @@ static void e1000e_send_verify(QE1000E *d, int *test_sockets,
QGuestAllocator *a
/* Wait for TX WB interrupt */
e1000e_wait_isr(d, E1000E_TX0_MSG_ID);
+ /* Read ICR to make it ready for next interrupt, assert TXQ0 cause */
+ g_assert(e1000e_macreg_read(d, E1000_ICR) & E1000_ICR_TXQ0);
/* Check DD bit */
g_assert_cmphex(le32_to_cpu(descr.upper.data) & E1000_TXD_STAT_DD, ==,
@@ -117,6 +119,8 @@ static void e1000e_receive_verify(QE1000E *d, int
*test_sockets, QGuestAllocator
/* Wait for TX WB interrupt */
e1000e_wait_isr(d, E1000E_RX0_MSG_ID);
+ /* Read ICR to make it ready for next interrupt, assert RXQ0 cause */
+ g_assert(e1000e_macreg_read(d, E1000_ICR) & E1000_ICR_RXQ0);
/* Check DD bit */
g_assert_cmphex(le32_to_cpu(descr.wb.upper.status_error) &
diff --git a/tests/qtest/igb-test.c b/tests/qtest/igb-test.c
index 3d397ea6973..fb77c5e507a 100644
--- a/tests/qtest/igb-test.c
+++ b/tests/qtest/igb-test.c
@@ -69,6 +69,8 @@ static void igb_send_verify(QE1000E *d, int *test_sockets,
QGuestAllocator *allo
/* Wait for TX WB interrupt */
e1000e_wait_isr(d, E1000E_TX0_MSG_ID);
+ /* Read EICR which clears it ready for next interrupt, assert TXQ0 cause */
+ g_assert(e1000e_macreg_read(d, E1000_EICR) & (1 << E1000E_TX0_MSG_ID));
/* Check DD bit */
g_assert_cmphex(le32_to_cpu(descr.wb.status) & E1000_TXD_STAT_DD, ==,
@@ -120,6 +122,8 @@ static void igb_receive_verify(QE1000E *d, int
*test_sockets, QGuestAllocator *a
/* Wait for TX WB interrupt */
e1000e_wait_isr(d, E1000E_RX0_MSG_ID);
+ /* Read EICR which clears it ready for next interrupt, assert RXQ0 cause */
+ g_assert(e1000e_macreg_read(d, E1000_EICR) & (1 << E1000E_RX0_MSG_ID));
/* Check DD bit */
g_assert_cmphex(le32_to_cpu(descr.wb.upper.status_error) &
--
2.45.2
