Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
---
include/tcg/tcg-opc.h | 3 +--
tcg/optimize.c | 30 ++++++------------------------
tcg/tcg-op.c | 4 ++--
tcg/tcg.c | 6 ++----
tcg/tci.c | 11 +++++------
tcg/tci/tcg-target.c.inc | 2 +-
6 files changed, 17 insertions(+), 39 deletions(-)
diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h
index 69fa55f3c6..9e148bb1b2 100644
--- a/include/tcg/tcg-opc.h
+++ b/include/tcg/tcg-opc.h
@@ -44,6 +44,7 @@ DEF(and, 1, 2, 0, TCG_OPF_INT)
DEF(andc, 1, 2, 0, TCG_OPF_INT)
DEF(eqv, 1, 2, 0, TCG_OPF_INT)
DEF(nand, 1, 2, 0, TCG_OPF_INT)
+DEF(neg, 1, 1, 0, TCG_OPF_INT)
DEF(nor, 1, 2, 0, TCG_OPF_INT)
DEF(or, 1, 2, 0, TCG_OPF_INT)
DEF(orc, 1, 2, 0, TCG_OPF_INT)
@@ -95,7 +96,6 @@ DEF(setcond2_i32, 1, 4, 1, 0)
DEF(bswap16_i32, 1, 1, 1, 0)
DEF(bswap32_i32, 1, 1, 1, 0)
DEF(not_i32, 1, 1, 0, 0)
-DEF(neg_i32, 1, 1, 0, 0)
DEF(clz_i32, 1, 2, 0, 0)
DEF(ctz_i32, 1, 2, 0, 0)
DEF(ctpop_i32, 1, 1, 0, 0)
@@ -145,7 +145,6 @@ DEF(bswap16_i64, 1, 1, 1, 0)
DEF(bswap32_i64, 1, 1, 1, 0)
DEF(bswap64_i64, 1, 1, 1, 0)
DEF(not_i64, 1, 1, 0, 0)
-DEF(neg_i64, 1, 1, 0, 0)
DEF(clz_i64, 1, 2, 0, 0)
DEF(ctz_i64, 1, 2, 0, 0)
DEF(ctpop_i64, 1, 1, 0, 0)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 2acff375b7..63d36afe69 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -466,7 +466,7 @@ static uint64_t do_constant_folding_2(TCGOpcode op,
uint64_t x, uint64_t y)
CASE_OP_32_64_VEC(not):
return ~x;
- CASE_OP_32_64(neg):
+ case INDEX_op_neg:
return -x;
case INDEX_op_andc:
@@ -2299,25 +2299,12 @@ static int fold_setcond_zmask(OptContext *ctx, TCGOp
*op, bool neg)
break;
}
if (convert) {
- TCGOpcode neg_opc;
-
if (!inv && !neg) {
return tcg_opt_gen_mov(ctx, op, op->args[0], op->args[1]);
}
- switch (ctx->type) {
- case TCG_TYPE_I32:
- neg_opc = INDEX_op_neg_i32;
- break;
- case TCG_TYPE_I64:
- neg_opc = INDEX_op_neg_i64;
- break;
- default:
- g_assert_not_reached();
- }
-
if (!inv) {
- op->opc = neg_opc;
+ op->opc = INDEX_op_neg;
} else if (neg) {
op->opc = INDEX_op_add;
op->args[2] = arg_new_constant(ctx, -1);
@@ -2333,7 +2320,7 @@ static int fold_setcond_zmask(OptContext *ctx, TCGOp *op,
bool neg)
static void fold_setcond_tst_pow2(OptContext *ctx, TCGOp *op, bool neg)
{
- TCGOpcode neg_opc, shr_opc;
+ TCGOpcode shr_opc;
TCGOpcode uext_opc = 0, sext_opc = 0;
TCGCond cond = op->args[3];
TCGArg ret, src1, src2;
@@ -2356,7 +2343,6 @@ static void fold_setcond_tst_pow2(OptContext *ctx, TCGOp
*op, bool neg)
switch (ctx->type) {
case TCG_TYPE_I32:
shr_opc = INDEX_op_shr_i32;
- neg_opc = INDEX_op_neg_i32;
if (TCG_TARGET_extract_valid(TCG_TYPE_I32, sh, 1)) {
uext_opc = INDEX_op_extract_i32;
}
@@ -2366,7 +2352,6 @@ static void fold_setcond_tst_pow2(OptContext *ctx, TCGOp
*op, bool neg)
break;
case TCG_TYPE_I64:
shr_opc = INDEX_op_shr_i64;
- neg_opc = INDEX_op_neg_i64;
if (TCG_TARGET_extract_valid(TCG_TYPE_I64, sh, 1)) {
uext_opc = INDEX_op_extract_i64;
}
@@ -2417,7 +2402,7 @@ static void fold_setcond_tst_pow2(OptContext *ctx, TCGOp
*op, bool neg)
op2->args[1] = ret;
op2->args[2] = arg_new_constant(ctx, 1);
} else if (neg) {
- op2 = tcg_op_insert_after(ctx->tcg, op, neg_opc, 2);
+ op2 = tcg_op_insert_after(ctx->tcg, op, INDEX_op_neg, 2);
op2->args[0] = ret;
op2->args[1] = ret;
}
@@ -2629,11 +2614,8 @@ static bool fold_sub_to_neg(OptContext *ctx, TCGOp *op)
switch (ctx->type) {
case TCG_TYPE_I32:
- neg_op = INDEX_op_neg_i32;
- have_neg = true;
- break;
case TCG_TYPE_I64:
- neg_op = INDEX_op_neg_i64;
+ neg_op = INDEX_op_neg;
have_neg = true;
break;
case TCG_TYPE_V64:
@@ -2983,7 +2965,7 @@ void tcg_optimize(TCGContext *s)
case INDEX_op_nand_vec:
done = fold_nand(&ctx, op);
break;
- CASE_OP_32_64(neg):
+ case INDEX_op_neg:
done = fold_neg(&ctx, op);
break;
case INDEX_op_nor:
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index 15faf4dc57..cb2eb9ae52 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -396,7 +396,7 @@ void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t
arg2)
void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg)
{
- tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg);
+ tcg_gen_op2_i32(INDEX_op_neg, ret, arg);
}
void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
@@ -1691,7 +1691,7 @@ void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1,
int64_t arg2)
void tcg_gen_neg_i64(TCGv_i64 ret, TCGv_i64 arg)
{
if (TCG_TARGET_REG_BITS == 64) {
- tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg);
+ tcg_gen_op2_i64(INDEX_op_neg, ret, arg);
} else {
TCGv_i32 zero = tcg_constant_i32(0);
tcg_gen_sub2_i32(TCGV_LOW(ret), TCGV_HIGH(ret),
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 2bbc4297c9..e7e8232219 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1009,8 +1009,7 @@ static const TCGOutOp * const all_outop[NB_OPS] = {
OUTOP(INDEX_op_andc, TCGOutOpBinary, outop_andc),
OUTOP(INDEX_op_eqv, TCGOutOpBinary, outop_eqv),
OUTOP(INDEX_op_nand, TCGOutOpBinary, outop_nand),
- OUTOP(INDEX_op_neg_i32, TCGOutOpUnary, outop_neg),
- OUTOP(INDEX_op_neg_i64, TCGOutOpUnary, outop_neg),
+ OUTOP(INDEX_op_neg, TCGOutOpUnary, outop_neg),
OUTOP(INDEX_op_nor, TCGOutOpBinary, outop_nor),
OUTOP(INDEX_op_or, TCGOutOpBinary, outop_or),
OUTOP(INDEX_op_orc, TCGOutOpBinary, outop_orc),
@@ -5456,8 +5455,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp
*op)
}
break;
- case INDEX_op_neg_i32:
- case INDEX_op_neg_i64:
+ case INDEX_op_neg:
{
const TCGOutOpUnary *out =
container_of(all_outop[op->opc], TCGOutOpUnary, base);
diff --git a/tcg/tci.c b/tcg/tci.c
index 1e176f03ee..b091dde7c8 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -577,6 +577,10 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState
*env,
tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = ~(regs[r1] | regs[r2]);
break;
+ case INDEX_op_neg:
+ tci_args_rr(insn, &r0, &r1);
+ regs[r0] = -regs[r1];
+ break;
/* Arithmetic operations (32 bit). */
@@ -707,10 +711,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState
*env,
regs[r0] = ~regs[r1];
break;
#endif
- CASE_32_64(neg)
- tci_args_rr(insn, &r0, &r1);
- regs[r0] = -regs[r1];
- break;
#if TCG_TARGET_REG_BITS == 64
/* Load/store operations (64 bit). */
@@ -1110,6 +1110,7 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
break;
case INDEX_op_mov:
+ case INDEX_op_neg:
case INDEX_op_ext_i32_i64:
case INDEX_op_extu_i32_i64:
case INDEX_op_bswap16_i32:
@@ -1119,8 +1120,6 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
case INDEX_op_bswap64_i64:
case INDEX_op_not_i32:
case INDEX_op_not_i64:
- case INDEX_op_neg_i32:
- case INDEX_op_neg_i64:
case INDEX_op_ctpop_i32:
case INDEX_op_ctpop_i64:
tci_args_rr(insn, &r0, &r1);
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index 45115d7e82..bb9dcbb75d 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -753,7 +753,7 @@ static const TCGOutOpBinary outop_xor = {
static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
{
- tcg_out_op_rr(s, glue(INDEX_op_neg_i,TCG_TARGET_REG_BITS), a0, a1);
+ tcg_out_op_rr(s, INDEX_op_neg, a0, a1);
}
static const TCGOutOpUnary outop_neg = {
--
2.43.0
