We can now handle the awkward i686 register constraints
by examining the MemOpIdx operand to qemu_st_*_i32.
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
---
include/tcg/tcg-opc.h | 6 ------
tcg/aarch64/tcg-target-has.h | 2 --
tcg/arm/tcg-target-has.h | 1 -
tcg/i386/tcg-target-con-str.h | 2 +-
tcg/i386/tcg-target-has.h | 6 ------
tcg/loongarch64/tcg-target-has.h | 1 -
tcg/mips/tcg-target-has.h | 1 -
tcg/ppc/tcg-target-has.h | 2 --
tcg/riscv/tcg-target-has.h | 1 -
tcg/s390x/tcg-target-has.h | 1 -
tcg/sparc64/tcg-target-has.h | 1 -
tcg/tci/tcg-target-has.h | 1 -
tcg/optimize.c | 2 --
tcg/tcg-op-ldst.c | 14 +++-----------
tcg/tcg.c | 6 ------
tcg/i386/tcg-target.c.inc | 25 +++++++++++++++++--------
16 files changed, 21 insertions(+), 51 deletions(-)
diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h
index efe2db5343..706d2a9794 100644
--- a/include/tcg/tcg-opc.h
+++ b/include/tcg/tcg-opc.h
@@ -182,12 +182,6 @@ DEF(qemu_ld_a64_i64, DATA64_ARGS, DATA64_ARGS, 1,
DEF(qemu_st_a64_i64, 0, DATA64_ARGS + DATA64_ARGS, 1,
TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT)
-/* Only used by i386 to cope with stupid register constraints. */
-DEF(qemu_st8_a32_i32, 0, 1 + 1, 1,
- TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
-DEF(qemu_st8_a64_i32, 0, 1 + DATA64_ARGS, 1,
- TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
-
/* Only for 64-bit hosts at the moment. */
DEF(qemu_ld_a32_i128, 2, 1, 1,
TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT)
diff --git a/tcg/aarch64/tcg-target-has.h b/tcg/aarch64/tcg-target-has.h
index 75344c301d..1ce5e8da5b 100644
--- a/tcg/aarch64/tcg-target-has.h
+++ b/tcg/aarch64/tcg-target-has.h
@@ -37,8 +37,6 @@
#define TCG_TARGET_HAS_not(T) 1
#define TCG_TARGET_HAS_orc(T) 1
-#define TCG_TARGET_HAS_qemu_st8_i32 0
-
/*
* Without FEAT_LSE2, we must use LDXP+STXP to implement atomic 128-bit load,
* which requires writable pages. We must defer to the helper for user-only,
diff --git a/tcg/arm/tcg-target-has.h b/tcg/arm/tcg-target-has.h
index 5ff32e96a4..2c8d25d60a 100644
--- a/tcg/arm/tcg-target-has.h
+++ b/tcg/arm/tcg-target-has.h
@@ -48,7 +48,6 @@ extern bool use_neon_instructions;
#define TCG_TARGET_HAS_not(T) 1
#define TCG_TARGET_HAS_orc(T) (T >= TCG_TYPE_V64)
-#define TCG_TARGET_HAS_qemu_st8_i32 0
#define TCG_TARGET_HAS_qemu_ldst_i128 0
#define TCG_TARGET_HAS_tst 1
diff --git a/tcg/i386/tcg-target-con-str.h b/tcg/i386/tcg-target-con-str.h
index 52142ab121..4ddc550f50 100644
--- a/tcg/i386/tcg-target-con-str.h
+++ b/tcg/i386/tcg-target-con-str.h
@@ -20,7 +20,7 @@ REGS('r', ALL_GENERAL_REGS)
REGS('x', ALL_VECTOR_REGS)
REGS('q', ALL_BYTEL_REGS) /* regs that can be used as a byte operand */
REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS) /* qemu_ld/st */
-REGS('s', ALL_BYTEL_REGS & ~SOFTMMU_RESERVE_REGS) /* qemu_st8_i32 data */
+REGS('s', ALL_BYTEL_REGS & ~SOFTMMU_RESERVE_REGS) /* qemu_st_i32 byte data
*/
/*
* Define constraint letters for constants:
diff --git a/tcg/i386/tcg-target-has.h b/tcg/i386/tcg-target-has.h
index 71277b3f28..61547a1269 100644
--- a/tcg/i386/tcg-target-has.h
+++ b/tcg/i386/tcg-target-has.h
@@ -49,12 +49,6 @@
#define TCG_TARGET_HAS_not(T) (T <= TCG_TYPE_REG || have_avx512vl)
#define TCG_TARGET_HAS_orc(T) (T >= TCG_TYPE_V64 && have_avx512vl)
-#if TCG_TARGET_REG_BITS == 64
-#define TCG_TARGET_HAS_qemu_st8_i32 0
-#else
-#define TCG_TARGET_HAS_qemu_st8_i32 1
-#endif
-
#define TCG_TARGET_HAS_qemu_ldst_i128 \
(TCG_TARGET_REG_BITS == 64 && (cpuinfo & CPUINFO_ATOMIC_VMOVDQA))
diff --git a/tcg/loongarch64/tcg-target-has.h b/tcg/loongarch64/tcg-target-has.h
index a141205322..9e47cf40d3 100644
--- a/tcg/loongarch64/tcg-target-has.h
+++ b/tcg/loongarch64/tcg-target-has.h
@@ -34,7 +34,6 @@
#define TCG_TARGET_HAS_not(T) 1
#define TCG_TARGET_HAS_orc(T) 1
-#define TCG_TARGET_HAS_qemu_st8_i32 0
#define TCG_TARGET_HAS_qemu_ldst_i128 (cpuinfo & CPUINFO_LSX)
#define TCG_TARGET_HAS_tst 0
diff --git a/tcg/mips/tcg-target-has.h b/tcg/mips/tcg-target-has.h
index f6ccba95e5..ee090724d9 100644
--- a/tcg/mips/tcg-target-has.h
+++ b/tcg/mips/tcg-target-has.h
@@ -63,7 +63,6 @@ extern bool use_mips32r2_instructions;
#define TCG_TARGET_HAS_not(T) 1
#define TCG_TARGET_HAS_orc(T) 0
-#define TCG_TARGET_HAS_qemu_st8_i32 0
#define TCG_TARGET_HAS_qemu_ldst_i128 0
#define TCG_TARGET_HAS_tst 0
diff --git a/tcg/ppc/tcg-target-has.h b/tcg/ppc/tcg-target-has.h
index 1247bc873c..348182e1e6 100644
--- a/tcg/ppc/tcg-target-has.h
+++ b/tcg/ppc/tcg-target-has.h
@@ -41,8 +41,6 @@
#define TCG_TARGET_HAS_not(T) 1
#define TCG_TARGET_HAS_orc(T) (T <= TCG_TYPE_REG || have_isa_2_07)
-#define TCG_TARGET_HAS_qemu_st8_i32 0
-
#define TCG_TARGET_HAS_qemu_ldst_i128 \
(TCG_TARGET_REG_BITS == 64 && have_isa_2_07)
diff --git a/tcg/riscv/tcg-target-has.h b/tcg/riscv/tcg-target-has.h
index 88c022256f..10e61edc45 100644
--- a/tcg/riscv/tcg-target-has.h
+++ b/tcg/riscv/tcg-target-has.h
@@ -34,7 +34,6 @@
#define TCG_TARGET_HAS_not(T) 1
#define TCG_TARGET_HAS_orc(T) (T <= TCG_TYPE_REG && (cpuinfo &
CPUINFO_ZBB))
-#define TCG_TARGET_HAS_qemu_st8_i32 0
#define TCG_TARGET_HAS_qemu_ldst_i128 0
#define TCG_TARGET_HAS_tst 0
diff --git a/tcg/s390x/tcg-target-has.h b/tcg/s390x/tcg-target-has.h
index 56d452bc7d..123b359a31 100644
--- a/tcg/s390x/tcg-target-has.h
+++ b/tcg/s390x/tcg-target-has.h
@@ -52,7 +52,6 @@ extern uint64_t s390_facilities[3];
#define TCG_TARGET_HAS_not(T) (T >= TCG_TYPE_V64 ||
HAVE_FACILITY(MISC_INSN_EXT3))
#define TCG_TARGET_HAS_orc(T) (T >= TCG_TYPE_V64 ?
HAVE_FACILITY(VECTOR_ENH1) : HAVE_FACILITY(MISC_INSN_EXT3))
-#define TCG_TARGET_HAS_qemu_st8_i32 0
#define TCG_TARGET_HAS_qemu_ldst_i128 1
#define TCG_TARGET_HAS_tst 1
diff --git a/tcg/sparc64/tcg-target-has.h b/tcg/sparc64/tcg-target-has.h
index e81f2bbe30..7e654240ad 100644
--- a/tcg/sparc64/tcg-target-has.h
+++ b/tcg/sparc64/tcg-target-has.h
@@ -38,7 +38,6 @@ extern bool use_vis3_instructions;
#define TCG_TARGET_HAS_not(T) 1
#define TCG_TARGET_HAS_orc(T) 1
-#define TCG_TARGET_HAS_qemu_st8_i32 0
#define TCG_TARGET_HAS_qemu_ldst_i128 0
#define TCG_TARGET_HAS_tst 1
diff --git a/tcg/tci/tcg-target-has.h b/tcg/tci/tcg-target-has.h
index 796769c574..3df463521d 100644
--- a/tcg/tci/tcg-target-has.h
+++ b/tcg/tci/tcg-target-has.h
@@ -32,7 +32,6 @@
#define TCG_TARGET_HAS_not(T) 1
#define TCG_TARGET_HAS_orc(T) 1
-#define TCG_TARGET_HAS_qemu_st8_i32 0
#define TCG_TARGET_HAS_qemu_ldst_i128 0
#define TCG_TARGET_HAS_tst 1
diff --git a/tcg/optimize.c b/tcg/optimize.c
index c55ad116bc..c591f93090 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -2914,8 +2914,6 @@ void tcg_optimize(TCGContext *s)
case INDEX_op_qemu_ld_a64_i128:
done = fold_qemu_ld_2reg(&ctx, op);
break;
- case INDEX_op_qemu_st8_a32_i32:
- case INDEX_op_qemu_st8_a64_i32:
case INDEX_op_qemu_st_a32_i32:
case INDEX_op_qemu_st_a64_i32:
case INDEX_op_qemu_st_a32_i64:
diff --git a/tcg/tcg-op-ldst.c b/tcg/tcg-op-ldst.c
index 77271e0193..b954e7379c 100644
--- a/tcg/tcg-op-ldst.c
+++ b/tcg/tcg-op-ldst.c
@@ -309,18 +309,10 @@ static void tcg_gen_qemu_st_i32_int(TCGv_i32 val, TCGTemp
*addr,
oi = make_memop_idx(memop, idx);
}
- if (TCG_TARGET_HAS_qemu_st8_i32 && (memop & MO_SIZE) == MO_8) {
- if (tcg_ctx->addr_type == TCG_TYPE_I32) {
- opc = INDEX_op_qemu_st8_a32_i32;
- } else {
- opc = INDEX_op_qemu_st8_a64_i32;
- }
+ if (tcg_ctx->addr_type == TCG_TYPE_I32) {
+ opc = INDEX_op_qemu_st_a32_i32;
} else {
- if (tcg_ctx->addr_type == TCG_TYPE_I32) {
- opc = INDEX_op_qemu_st_a32_i32;
- } else {
- opc = INDEX_op_qemu_st_a64_i32;
- }
+ opc = INDEX_op_qemu_st_a64_i32;
}
gen_ldst(opc, TCG_TYPE_I32, tcgv_i32_temp(val), NULL, addr, oi);
plugin_gen_mem_callbacks_i32(val, NULL, addr, orig_oi, QEMU_PLUGIN_MEM_W);
diff --git a/tcg/tcg.c b/tcg/tcg.c
index ba01e0a580..e7bb7a4d69 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -2159,10 +2159,6 @@ bool tcg_op_supported(TCGOpcode op, TCGType type)
case INDEX_op_qemu_st_a64_i64:
return true;
- case INDEX_op_qemu_st8_a32_i32:
- case INDEX_op_qemu_st8_a64_i32:
- return TCG_TARGET_HAS_qemu_st8_i32;
-
case INDEX_op_qemu_ld_a32_i128:
case INDEX_op_qemu_ld_a64_i128:
case INDEX_op_qemu_st_a32_i128:
@@ -2840,8 +2836,6 @@ void tcg_dump_ops(TCGContext *s, FILE *f, bool have_prefs)
case INDEX_op_qemu_ld_a64_i32:
case INDEX_op_qemu_st_a32_i32:
case INDEX_op_qemu_st_a64_i32:
- case INDEX_op_qemu_st8_a32_i32:
- case INDEX_op_qemu_st8_a64_i32:
case INDEX_op_qemu_ld_a32_i64:
case INDEX_op_qemu_ld_a64_i64:
case INDEX_op_qemu_st_a32_i64:
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index 89b2eaf0cd..bee3e6b8c2 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -2481,7 +2481,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg
datalo, TCGReg datahi,
switch (memop & MO_SIZE) {
case MO_8:
- /* This is handled with constraints on INDEX_op_qemu_st8_i32. */
+ /* This is handled with constraints on INDEX_op_qemu_st_i32. */
tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || datalo < 4);
tcg_out_modrm_sib_offset(s, OPC_MOVB_EvGv + P_REXB_R + h.seg,
datalo, h.base, h.index, 0, h.ofs);
@@ -2934,14 +2934,12 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode
opc,
break;
case INDEX_op_qemu_st_a64_i32:
- case INDEX_op_qemu_st8_a64_i32:
if (TCG_TARGET_REG_BITS == 32) {
tcg_out_qemu_st(s, a0, -1, a1, a2, args[3], TCG_TYPE_I32);
break;
}
/* fall through */
case INDEX_op_qemu_st_a32_i32:
- case INDEX_op_qemu_st8_a32_i32:
tcg_out_qemu_st(s, a0, -1, a1, -1, a2, TCG_TYPE_I32);
break;
case INDEX_op_qemu_st_a32_i64:
@@ -3807,13 +3805,24 @@ static TCGConstraintSetIndex tcg_target_op_def(const
TCGOp *op)
return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L) : C_O1_I2(r, L, L);
case INDEX_op_qemu_st_a32_i32:
+ if (TCG_TARGET_REG_BITS == 32) {
+ MemOpIdx oi = op->args[2];
+ MemOp mop = get_memop(oi);
+ if ((mop & MO_SIZE) == MO_8) {
+ return C_O0_I2(s, L);
+ }
+ }
return C_O0_I2(L, L);
case INDEX_op_qemu_st_a64_i32:
- return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(L, L) : C_O0_I3(L, L, L);
- case INDEX_op_qemu_st8_a32_i32:
- return C_O0_I2(s, L);
- case INDEX_op_qemu_st8_a64_i32:
- return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(s, L) : C_O0_I3(s, L, L);
+ if (TCG_TARGET_REG_BITS == 32) {
+ MemOpIdx oi = op->args[3];
+ MemOp mop = get_memop(oi);
+ if ((mop & MO_SIZE) == MO_8) {
+ return C_O0_I3(s, L, L);
+ }
+ return C_O0_I3(L, L, L);
+ }
+ return C_O0_I2(L, L);
case INDEX_op_qemu_ld_a32_i64:
return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L) : C_O2_I1(r, r, L);
--
2.43.0
