Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
---
include/tcg/tcg-opc.h | 3 +--
tcg/optimize.c | 2 +-
tcg/tcg-op.c | 8 ++++----
tcg/tcg.c | 3 +--
tcg/tci.c | 12 ++++--------
tcg/aarch64/tcg-target.c.inc | 6 ++----
tcg/arm/tcg-target.c.inc | 4 ++--
tcg/i386/tcg-target.c.inc | 5 ++---
tcg/loongarch64/tcg-target.c.inc | 14 +++++++-------
tcg/mips/tcg-target.c.inc | 16 ++++++++--------
tcg/ppc/tcg-target.c.inc | 23 ++++++++++-------------
tcg/s390x/tcg-target.c.inc | 5 ++---
tcg/tci/tcg-target.c.inc | 5 ++---
13 files changed, 46 insertions(+), 60 deletions(-)
diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h
index e39788bc14..d390d639ee 100644
--- a/include/tcg/tcg-opc.h
+++ b/include/tcg/tcg-opc.h
@@ -71,6 +71,7 @@ DEF(rotl, 1, 2, 0, TCG_OPF_INT)
DEF(rotr, 1, 2, 0, TCG_OPF_INT)
DEF(extract, 1, 1, 2, TCG_OPF_INT)
DEF(sextract, 1, 1, 2, TCG_OPF_INT)
+DEF(deposit, 1, 2, 2, TCG_OPF_INT)
DEF(brcond, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_COND_BRANCH | TCG_OPF_INT)
DEF(setcond, 1, 2, 1, TCG_OPF_INT)
@@ -81,7 +82,6 @@ DEF(movcond, 1, 4, 1, TCG_OPF_INT)
DEF(ld_i32, 1, 1, 2, 0)
DEF(st_i32, 0, 2, 2, 0)
/* shifts/rotates */
-DEF(deposit_i32, 1, 2, 2, 0)
DEF(extract2_i32, 1, 2, 1, 0)
DEF(brcond2_i32, 0, 4, 2, TCG_OPF_BB_END | TCG_OPF_COND_BRANCH)
@@ -97,7 +97,6 @@ DEF(ctpop_i32, 1, 1, 0, 0)
DEF(ld_i64, 1, 1, 2, 0)
DEF(st_i64, 0, 2, 2, 0)
/* shifts/rotates */
-DEF(deposit_i64, 1, 2, 2, 0)
DEF(extract2_i64, 1, 2, 1, 0)
/* size changing ops */
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 0240831343..25ab293a73 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -2746,7 +2746,7 @@ void tcg_optimize(TCGContext *s)
CASE_OP_32_64(ctpop):
done = fold_ctpop(&ctx, op);
break;
- CASE_OP_32_64(deposit):
+ case INDEX_op_deposit:
done = fold_deposit(&ctx, op);
break;
case INDEX_op_div:
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index c9c806b543..65a6031eaf 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -907,7 +907,7 @@ void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1,
TCGv_i32 arg2,
return;
}
if (TCG_TARGET_deposit_valid(TCG_TYPE_I32, ofs, len)) {
- tcg_gen_op5ii_i32(INDEX_op_deposit_i32, ret, arg1, arg2, ofs, len);
+ tcg_gen_op5ii_i32(INDEX_op_deposit, ret, arg1, arg2, ofs, len);
return;
}
@@ -953,7 +953,7 @@ void tcg_gen_deposit_z_i32(TCGv_i32 ret, TCGv_i32 arg,
tcg_gen_andi_i32(ret, arg, (1u << len) - 1);
} else if (TCG_TARGET_deposit_valid(TCG_TYPE_I32, ofs, len)) {
TCGv_i32 zero = tcg_constant_i32(0);
- tcg_gen_op5ii_i32(INDEX_op_deposit_i32, ret, zero, arg, ofs, len);
+ tcg_gen_op5ii_i32(INDEX_op_deposit, ret, zero, arg, ofs, len);
} else {
/*
* To help two-operand hosts we prefer to zero-extend first,
@@ -2553,7 +2553,7 @@ void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1,
TCGv_i64 arg2,
if (TCG_TARGET_REG_BITS == 64) {
if (TCG_TARGET_deposit_valid(TCG_TYPE_I64, ofs, len)) {
- tcg_gen_op5ii_i64(INDEX_op_deposit_i64, ret, arg1, arg2, ofs, len);
+ tcg_gen_op5ii_i64(INDEX_op_deposit, ret, arg1, arg2, ofs, len);
return;
}
if (TCG_TARGET_HAS_extract2(TCG_TYPE_I64)) {
@@ -2614,7 +2614,7 @@ void tcg_gen_deposit_z_i64(TCGv_i64 ret, TCGv_i64 arg,
} else if (TCG_TARGET_REG_BITS == 64 &&
TCG_TARGET_deposit_valid(TCG_TYPE_I64, ofs, len)) {
TCGv_i64 zero = tcg_constant_i64(0);
- tcg_gen_op5ii_i64(INDEX_op_deposit_i64, ret, zero, arg, ofs, len);
+ tcg_gen_op5ii_i64(INDEX_op_deposit, ret, zero, arg, ofs, len);
} else {
if (TCG_TARGET_REG_BITS == 32) {
if (ofs >= 32) {
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 72b062e76d..77f28147a1 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -2192,6 +2192,7 @@ bool tcg_op_supported(TCGOpcode op, TCGType type)
case INDEX_op_add:
case INDEX_op_and:
case INDEX_op_brcond:
+ case INDEX_op_deposit:
case INDEX_op_extract:
case INDEX_op_mov:
case INDEX_op_movcond:
@@ -2209,7 +2210,6 @@ bool tcg_op_supported(TCGOpcode op, TCGType type)
case INDEX_op_ld_i32:
case INDEX_op_st_i32:
- case INDEX_op_deposit_i32:
return true;
case INDEX_op_add2:
@@ -2269,7 +2269,6 @@ bool tcg_op_supported(TCGOpcode op, TCGType type)
case INDEX_op_extu_i32_i64:
case INDEX_op_extrl_i64_i32:
case INDEX_op_extrh_i64_i32:
- case INDEX_op_deposit_i64:
return TCG_TARGET_REG_BITS == 64;
case INDEX_op_extract2_i64:
diff --git a/tcg/tci.c b/tcg/tci.c
index 063d39adfa..9cc983ca1a 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -38,6 +38,7 @@
#define extract_tr glue(extract, TCG_TARGET_REG_BITS)
#define sextract_tr glue(sextract, TCG_TARGET_REG_BITS)
+#define deposit_tr glue(deposit, TCG_TARGET_REG_BITS)
__thread uintptr_t tci_tb_ptr;
@@ -646,9 +647,9 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState
*env,
/* Shift/rotate operations (32 bit). */
- case INDEX_op_deposit_i32:
+ case INDEX_op_deposit:
tci_args_rrrbb(insn, &r0, &r1, &r2, &pos, &len);
- regs[r0] = deposit32(regs[r1], pos, len, regs[r2]);
+ regs[r0] = deposit_tr(regs[r1], pos, len, regs[r2]);
break;
case INDEX_op_extract:
tci_args_rrbb(insn, &r0, &r1, &pos, &len);
@@ -760,10 +761,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState
*env,
/* Shift/rotate operations (64 bit). */
- case INDEX_op_deposit_i64:
- tci_args_rrrbb(insn, &r0, &r1, &r2, &pos, &len);
- regs[r0] = deposit64(regs[r1], pos, len, regs[r2]);
- break;
case INDEX_op_ext_i32_i64:
tci_args_rr(insn, &r0, &r1);
regs[r0] = (int32_t)regs[r1];
@@ -1069,8 +1066,7 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
op_name, str_r(r0), str_r(r1), str_r(r2));
break;
- case INDEX_op_deposit_i32:
- case INDEX_op_deposit_i64:
+ case INDEX_op_deposit:
tci_args_rrrbb(insn, &r0, &r1, &r2, &pos, &len);
info->fprintf_func(info->stream, "%-12s %s, %s, %s, %d, %d",
op_name, str_r(r0), str_r(r1), str_r(r2), pos, len);
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index bc695aa760..57f4e05b5c 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -2409,8 +2409,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
TCGType ext,
}
break;
- case INDEX_op_deposit_i64:
- case INDEX_op_deposit_i32:
+ case INDEX_op_deposit:
tcg_out_dep(s, ext, a0, REG0(2), args[3], args[4]);
break;
@@ -2996,8 +2995,7 @@ static TCGConstraintSetIndex tcg_target_op_def(const
TCGOp *op)
case INDEX_op_qemu_st_a64_i128:
return C_O0_I3(rZ, rZ, r);
- case INDEX_op_deposit_i32:
- case INDEX_op_deposit_i64:
+ case INDEX_op_deposit:
return C_O1_I2(r, 0, rZ);
case INDEX_op_extract2_i32:
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index 3b89a6c60e..1bf020ed67 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -2123,7 +2123,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
TCGType type,
tcg_out_bswap32(s, COND_AL, args[0], args[1]);
break;
- case INDEX_op_deposit_i32:
+ case INDEX_op_deposit:
tcg_out_deposit(s, COND_AL, args[0], args[2],
args[3], args[4], const_args[2]);
break;
@@ -2227,7 +2227,7 @@ static TCGConstraintSetIndex tcg_target_op_def(const
TCGOp *op)
case INDEX_op_brcond:
return C_O0_I2(r, rIN);
- case INDEX_op_deposit_i32:
+ case INDEX_op_deposit:
return C_O1_I2(r, 0, rZ);
case INDEX_op_extract2_i32:
return C_O1_I2(r, rZ, rZ);
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index 75a3b4641a..917775b7f6 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -3010,7 +3010,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
TCGType type,
break;
#endif
- OP_32_64(deposit):
+ case INDEX_op_deposit:
if (args[3] == 0 && args[4] == 8) {
/* load bits 0..7 */
if (const_a2) {
@@ -3730,8 +3730,7 @@ static TCGConstraintSetIndex tcg_target_op_def(const
TCGOp *op)
case INDEX_op_extract2_i64:
return C_O1_I2(r, 0, r);
- case INDEX_op_deposit_i32:
- case INDEX_op_deposit_i64:
+ case INDEX_op_deposit:
return C_O1_I2(q, 0, qi);
case INDEX_op_setcond:
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index d22223bb45..563299381a 100644
--- a/tcg/loongarch64/tcg-target.c.inc
+++ b/tcg/loongarch64/tcg-target.c.inc
@@ -1392,11 +1392,12 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
TCGType type,
}
break;
- case INDEX_op_deposit_i32:
- tcg_out_opc_bstrins_w(s, a0, a2, args[3], args[3] + args[4] - 1);
- break;
- case INDEX_op_deposit_i64:
- tcg_out_opc_bstrins_d(s, a0, a2, args[3], args[3] + args[4] - 1);
+ case INDEX_op_deposit:
+ if (type == TCG_TYPE_I32) {
+ tcg_out_opc_bstrins_w(s, a0, a2, args[3], args[3] + args[4] - 1);
+ } else {
+ tcg_out_opc_bstrins_d(s, a0, a2, args[3], args[3] + args[4] - 1);
+ }
break;
case INDEX_op_bswap16_i32:
@@ -2283,8 +2284,7 @@ static TCGConstraintSetIndex tcg_target_op_def(const
TCGOp *op)
case INDEX_op_ctz_i64:
return C_O1_I2(r, r, rW);
- case INDEX_op_deposit_i32:
- case INDEX_op_deposit_i64:
+ case INDEX_op_deposit:
/* Must deposit into the same register as input */
return C_O1_I2(r, 0, rZ);
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index 143348ab2e..d74bcdb96f 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -2014,12 +2014,13 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
TCGType type,
tcg_out_clz(s, OPC_DCLZ, OPC_DCLZ_R6, 64, a0, a1, a2);
break;
- case INDEX_op_deposit_i32:
- tcg_out_opc_bf(s, OPC_INS, a0, a2, args[3] + args[4] - 1, args[3]);
- break;
- case INDEX_op_deposit_i64:
- tcg_out_opc_bf64(s, OPC_DINS, OPC_DINSM, OPC_DINSU, a0, a2,
- args[3] + args[4] - 1, args[3]);
+ case INDEX_op_deposit:
+ if (type == TCG_TYPE_I32) {
+ tcg_out_opc_bf(s, OPC_INS, a0, a2, args[3] + args[4] - 1, args[3]);
+ } else {
+ tcg_out_opc_bf64(s, OPC_DINS, OPC_DINSM, OPC_DINSU, a0, a2,
+ args[3] + args[4] - 1, args[3]);
+ }
break;
case INDEX_op_extract:
@@ -2196,8 +2197,7 @@ static TCGConstraintSetIndex tcg_target_op_def(const
TCGOp *op)
case INDEX_op_clz_i64:
return C_O1_I2(r, r, rWZ);
- case INDEX_op_deposit_i32:
- case INDEX_op_deposit_i64:
+ case INDEX_op_deposit:
return C_O1_I2(r, 0, rZ);
case INDEX_op_brcond:
return C_O0_I2(rZ, rZ);
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index c2b53c79f7..c501b1a205 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -3353,19 +3353,17 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
TCGType type,
tcg_out_bswap64(s, args[0], args[1]);
break;
- case INDEX_op_deposit_i32:
- if (const_args[2]) {
- uint32_t mask = ((2u << (args[4] - 1)) - 1) << args[3];
- tcg_out_andi32(s, args[0], args[0], ~mask);
- } else {
- tcg_out_rlw(s, RLWIMI, args[0], args[2], args[3],
- 32 - args[3] - args[4], 31 - args[3]);
- }
- break;
- case INDEX_op_deposit_i64:
+ case INDEX_op_deposit:
if (const_args[2]) {
uint64_t mask = ((2ull << (args[4] - 1)) - 1) << args[3];
- tcg_out_andi64(s, args[0], args[0], ~mask);
+ if (type == TCG_TYPE_I32) {
+ tcg_out_andi32(s, args[0], args[0], ~mask);
+ } else {
+ tcg_out_andi64(s, args[0], args[0], ~mask);
+ }
+ } else if (type == TCG_TYPE_I32) {
+ tcg_out_rlw(s, RLWIMI, args[0], args[2], args[3],
+ 32 - args[3] - args[4], 31 - args[3]);
} else {
tcg_out_rld(s, RLDIMI, args[0], args[2], args[3],
64 - args[3] - args[4]);
@@ -4166,8 +4164,7 @@ static TCGConstraintSetIndex tcg_target_op_def(const
TCGOp *op)
case INDEX_op_movcond:
return C_O1_I4(r, r, rC, rZ, rZ);
- case INDEX_op_deposit_i32:
- case INDEX_op_deposit_i64:
+ case INDEX_op_deposit:
return C_O1_I2(r, 0, rZ);
case INDEX_op_brcond2_i32:
return C_O0_I4(r, r, ri, ri);
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
index ac7af3f854..3ee364b27f 100644
--- a/tcg/s390x/tcg-target.c.inc
+++ b/tcg/s390x/tcg-target.c.inc
@@ -2655,7 +2655,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
TCGType type,
tcg_out_sh64(s, RSY_SRLG, args[0], args[1], TCG_REG_NONE, 32);
break;
- OP_32_64(deposit):
+ case INDEX_op_deposit:
a0 = args[0], a1 = args[1], a2 = args[2];
if (const_args[1]) {
tgen_deposit(s, a0, a2, args[3], args[4], 1);
@@ -3248,8 +3248,7 @@ static TCGConstraintSetIndex tcg_target_op_def(const
TCGOp *op)
case INDEX_op_qemu_st_a64_i128:
return C_O0_I3(o, m, r);
- case INDEX_op_deposit_i32:
- case INDEX_op_deposit_i64:
+ case INDEX_op_deposit:
return C_O1_I2(r, rZ, r);
case INDEX_op_movcond:
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index e4f227fb4b..3a3fef8679 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -86,8 +86,7 @@ static TCGConstraintSetIndex tcg_target_op_def(const TCGOp
*op)
case INDEX_op_rotl:
case INDEX_op_rotr:
case INDEX_op_setcond:
- case INDEX_op_deposit_i32:
- case INDEX_op_deposit_i64:
+ case INDEX_op_deposit:
case INDEX_op_clz_i32:
case INDEX_op_clz_i64:
case INDEX_op_ctz_i32:
@@ -749,7 +748,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
TCGType type,
}
break;
- CASE_32_64(deposit) /* Optional (TCG_TARGET_HAS_deposit_*). */
+ case INDEX_op_deposit:
tcg_out_op_rrrbb(s, opc, args[0], args[1], args[2], args[3], args[4]);
break;
--
2.43.0
