Accept byte and word extensions with the extract opcodes.
This is preparatory to removing the specialized extracts.
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
---
tcg/riscv/tcg-target-has.h | 39 ++++++++++++++++++++++++++++++++++----
tcg/riscv/tcg-target.c.inc | 34 +++++++++++++++++++++++++++++++++
2 files changed, 69 insertions(+), 4 deletions(-)
diff --git a/tcg/riscv/tcg-target-has.h b/tcg/riscv/tcg-target-has.h
index 08096d0625..efebc46109 100644
--- a/tcg/riscv/tcg-target-has.h
+++ b/tcg/riscv/tcg-target-has.h
@@ -34,8 +34,8 @@
#define TCG_TARGET_HAS_orc(T) (T <= TCG_TYPE_REG && (cpuinfo &
CPUINFO_ZBB))
#define TCG_TARGET_HAS_deposit_i32 0
-#define TCG_TARGET_HAS_extract_i32 0
-#define TCG_TARGET_HAS_sextract_i32 0
+#define TCG_TARGET_HAS_extract_i32 1
+#define TCG_TARGET_HAS_sextract_i32 1
#define TCG_TARGET_HAS_extract2_i32 0
#define TCG_TARGET_HAS_ext8s_i32 1
#define TCG_TARGET_HAS_ext16s_i32 1
@@ -46,8 +46,8 @@
#define TCG_TARGET_HAS_qemu_st8_i32 0
#define TCG_TARGET_HAS_deposit_i64 0
-#define TCG_TARGET_HAS_extract_i64 0
-#define TCG_TARGET_HAS_sextract_i64 0
+#define TCG_TARGET_HAS_extract_i64 1
+#define TCG_TARGET_HAS_sextract_i64 1
#define TCG_TARGET_HAS_extract2_i64 0
#define TCG_TARGET_HAS_extr_i64_i32 1
#define TCG_TARGET_HAS_ext8s_i64 1
@@ -81,4 +81,35 @@
#define TCG_TARGET_HAS_tst_vec 0
+static inline bool
+tcg_target_extract_valid(TCGType type, unsigned ofs, unsigned len)
+{
+ if (ofs == 0) {
+ switch (len) {
+ case 16:
+ return cpuinfo & CPUINFO_ZBB;
+ case 32:
+ return (cpuinfo & CPUINFO_ZBA) && type == TCG_TYPE_I64;
+ }
+ }
+ return false;
+}
+#define TCG_TARGET_extract_valid tcg_target_extract_valid
+
+static inline bool
+tcg_target_sextract_valid(TCGType type, unsigned ofs, unsigned len)
+{
+ if (ofs == 0) {
+ switch (len) {
+ case 8:
+ case 16:
+ return cpuinfo & CPUINFO_ZBB;
+ case 32:
+ return type == TCG_TYPE_I64;
+ }
+ }
+ return false;
+}
+#define TCG_TARGET_sextract_valid tcg_target_sextract_valid
+
#endif
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index 7d1bba100a..8122187665 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -2343,6 +2343,36 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
tcg_out_mb(s, a0);
break;
+ case INDEX_op_extract_i64:
+ if (a2 == 0 && args[3] == 32) {
+ tcg_out_ext32u(s, a0, a1);
+ break;
+ }
+ /* FALLTHRU */
+ case INDEX_op_extract_i32:
+ if (a2 == 0 && args[3] == 16) {
+ tcg_out_ext16u(s, a0, a1);
+ } else {
+ g_assert_not_reached();
+ }
+ break;
+
+ case INDEX_op_sextract_i64:
+ if (a2 == 0 && args[3] == 32) {
+ tcg_out_ext32s(s, a0, a1);
+ break;
+ }
+ /* FALLTHRU */
+ case INDEX_op_sextract_i32:
+ if (a2 == 0 && args[3] == 8) {
+ tcg_out_ext8s(s, TCG_TYPE_REG, a0, a1);
+ } else if (a2 == 0 && args[3] == 16) {
+ tcg_out_ext16s(s, TCG_TYPE_REG, a0, a1);
+ } else {
+ g_assert_not_reached();
+ }
+ break;
+
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
case INDEX_op_mov_i64:
case INDEX_op_call: /* Always emitted via tcg_out_call. */
@@ -2619,6 +2649,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode
op)
case INDEX_op_extrl_i64_i32:
case INDEX_op_extrh_i64_i32:
case INDEX_op_ext_i32_i64:
+ case INDEX_op_extract_i32:
+ case INDEX_op_extract_i64:
+ case INDEX_op_sextract_i32:
+ case INDEX_op_sextract_i64:
case INDEX_op_bswap16_i32:
case INDEX_op_bswap32_i32:
case INDEX_op_bswap16_i64:
--
2.43.0
