Hi, Let's add trace capabilities in riscv_raise_exception() to allow users of qemu-riscv(32/64) to have a little more information when a SIGILL occurs. This is done in patch 2.
Patch 1 is a "look and feel" patch that I figured was worth doing. Daniel Henrique Barboza (2): target/riscv: use RISCVException enum in exception helpers target/riscv: add trace in riscv_raise_exception() target/riscv/cpu.h | 3 ++- target/riscv/op_helper.c | 9 ++++++++- target/riscv/trace-events | 3 +++ target/riscv/translate.c | 2 +- 4 files changed, 14 insertions(+), 3 deletions(-) -- 2.47.1
