On Thu, Dec 5, 2024 at 5:38 PM MollyChen <xia...@iscas.ac.cn> wrote:
>
> Add a CPU entry for the RV64 XiangShan NANHU CPU which
> supports single-core and dual-core configurations. More
> details can be found at
> https://docs.xiangshan.cc/zh-cn/latest/integration/overview
>
> Signed-off-by: MollyChen <xia...@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> target/riscv/cpu-qom.h | 1 +
> target/riscv/cpu.c | 29 +++++++++++++++++++++++++++++
> 2 files changed, 30 insertions(+)
>
> diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
> index 6547642287..d56b067bf2 100644
> --- a/target/riscv/cpu-qom.h
> +++ b/target/riscv/cpu-qom.h
> @@ -50,6 +50,7 @@
> #define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906")
> #define TYPE_RISCV_CPU_VEYRON_V1 RISCV_CPU_TYPE_NAME("veyron-v1")
> #define TYPE_RISCV_CPU_TT_ASCALON RISCV_CPU_TYPE_NAME("tt-ascalon")
> +#define TYPE_RISCV_CPU_XIANGSHAN_NANHU
> RISCV_CPU_TYPE_NAME("xiangshan-nanhu")
> #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host")
>
> OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 8447ad0dfb..38baaa39f8 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -645,6 +645,34 @@ static void rv64_tt_ascalon_cpu_init(Object *obj)
> #endif
> }
>
> +static void rv64_xiangshan_nanhu_cpu_init(Object *obj)
> +{
> + CPURISCVState *env = &RISCV_CPU(obj)->env;
> + RISCVCPU *cpu = RISCV_CPU(obj);
> +
> + riscv_cpu_set_misa_ext(env, RVG | RVC | RVB | RVS | RVU);
> + env->priv_ver = PRIV_VERSION_1_12_0;
> +
> + /* Enable ISA extensions */
> + cpu->cfg.ext_zbc = true;
> + cpu->cfg.ext_zbkb = true;
> + cpu->cfg.ext_zbkc = true;
> + cpu->cfg.ext_zbkx = true;
> + cpu->cfg.ext_zknd = true;
> + cpu->cfg.ext_zkne = true;
> + cpu->cfg.ext_zknh = true;
> + cpu->cfg.ext_zksed = true;
> + cpu->cfg.ext_zksh = true;
> + cpu->cfg.ext_svinval = true;
> +
> + cpu->cfg.mmu = true;
> + cpu->cfg.pmp = true;
> +
> +#ifndef CONFIG_USER_ONLY
> + set_satp_mode_max_supported(cpu, VM_1_10_SV39);
> +#endif
> +}
> +
> #ifdef CONFIG_TCG
> static void rv128_base_cpu_init(Object *obj)
> {
> @@ -3050,6 +3078,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_THEAD_C906, MXL_RV64,
> rv64_thead_c906_cpu_init),
> DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_TT_ASCALON, MXL_RV64,
> rv64_tt_ascalon_cpu_init),
> DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, MXL_RV64,
> rv64_veyron_v1_cpu_init),
> + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_XIANGSHAN_NANHU, MXL_RV64,
> rv64_xiangshan_nanhu_cpu_init),
> #ifdef CONFIG_TCG
> DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, MXL_RV128,
> rv128_base_cpu_init),
> #endif /* CONFIG_TCG */
> --
> 2.34.1
>
>
