HOMER memory implements some dummy registers that return a nonsense
value to satisfy skiboot accesses caused by "SLW" init and register
save/restore programming that has never worked under QEMU:
[ 0.265000943,3] SLW: Failed to set HRMOR for CPU 0,RC=0x1
[ 0.265356988,3] Disabling deep stop states
To simplify a later change to implement HOMER as a RAM area, make
these return zero, which has the same result.
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
---
hw/ppc/pnv_homer.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/pnv_homer.c b/hw/ppc/pnv_homer.c
index 9aedc08cc00..658b0186a38 100644
--- a/hw/ppc/pnv_homer.c
+++ b/hw/ppc/pnv_homer.c
@@ -89,7 +89,7 @@ static uint64_t pnv_power8_homer_read(void *opaque, hwaddr
addr,
case PNV8_OCC_VCS_VOLTAGE_IDENTIFIER:
return 1;
case PNV8_OCC_PSTATE_DATA:
- return 0x1000000000000000;
+ return 0;
/* P8 frequency for 0, 1, and 2 pstates */
case PNV8_OCC_PSTATE_ZERO_FREQUENCY:
case PNV8_OCC_PSTATE_ONE_FREQUENCY:
@@ -259,7 +259,7 @@ static uint64_t pnv_power9_homer_read(void *opaque, hwaddr
addr,
return 0x01;
case PNV9_CHIP_HOMER_BASE:
case PNV9_CHIP_HOMER_IMAGE_POINTER:
- return 0x1000000000000000;
+ return 0;
case PNV9_DYNAMIC_DATA_STATE:
return 0x03; /* active */
}
--
2.45.2
