On Sun, 1 Dec 2024 at 15:19, Richard Henderson
<richard.hender...@linaro.org> wrote:
>
> Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
> ---
> target/arm/tcg/translate-a64.c | 61 ++++++++++++++++++----------------
> target/arm/tcg/a64.decode | 7 ++++
> 2 files changed, 39 insertions(+), 29 deletions(-)
>
> diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
> index 613dcdb9a2..31272c1878 100644
> --- a/target/arm/tcg/translate-a64.c
> +++ b/target/arm/tcg/translate-a64.c
> @@ -9153,6 +9153,28 @@ static bool trans_SHLL_v(DisasContext *s, arg_qrr_e *a)
> return true;
> }
>
> +static bool do_fabs_fneg_v(DisasContext *s, arg_qrr_e *a, bool neg)
> +{
> + int check = fp_access_check_vector_hsd(s, a->q, a->esz);
> + uint64_t sign;
> +
> + if (check <= 0) {
> + return check == 0;
> + }
> +
> + sign = 1ull << ((8 << a->esz) - 1);
> + if (neg) {
> + gen_gvec_fn2i(s, a->q, a->rd, a->rn, sign,
> + tcg_gen_gvec_xori, a->esz);
> + } else {
> + gen_gvec_fn2i(s, a->q, a->rd, a->rn, sign - 1,
> + tcg_gen_gvec_andi, a->esz);
> + }
> + return true;
> +}
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Annoying FEAT_AFP wrinkle: for FPCR.AH=1 we will need to make
fabs and fneg not flip the sign bit for NaNs. I guess that means
AH will need to be a tbflags bit so we can generate the nice
vector code for AH=0 and fall back to something else for AH=1.
thanks
-- PMM
