On Sun, 1 Dec 2024 at 15:08, Richard Henderson
<richard.hender...@linaro.org> wrote:
>
> This includes SCVTF, UCVTF, FCVT{N,P,M,Z,A}{S,U}.
> Remove disas_fp_fixed_conv as those were the last insns
> decoded by that function.
>
> Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
> +static void do_fcvt_scalar(DisasContext *s, MemOp out, MemOp esz,
> + TCGv_i64 tcg_out, int shift, int rn,
> + ARMFPRounding rmode)
> +{
> + TCGv_ptr tcg_fpstatus;
> + TCGv_i32 tcg_shift, tcg_rmode, tcg_single;
> +
> + tcg_fpstatus = fpstatus_ptr(esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
> + tcg_shift = tcg_constant_i32(shift);
> + tcg_rmode = gen_set_rmode(rmode, tcg_fpstatus);
> +
> + switch (esz) {
> + case MO_64:
> + read_vec_element(s, tcg_out, rn, 0, MO_64);
> + switch (out) {
> + case MO_64 | MO_SIGN:
> + gen_helper_vfp_tosqd(tcg_out, tcg_out, tcg_shift, tcg_fpstatus);
> + break;
> + case MO_64:
> + gen_helper_vfp_touqd(tcg_out, tcg_out, tcg_shift, tcg_fpstatus);
> + break;
> + case MO_32 | MO_SIGN:
> + gen_helper_vfp_tosld(tcg_out, tcg_out, tcg_shift, tcg_fpstatus);
> + break;
> + case MO_32:
> + gen_helper_vfp_tould(tcg_out, tcg_out, tcg_shift, tcg_fpstatus);
> + break;
> + default:
> + g_assert_not_reached();
> + }
> + break;
> +
> + case MO_32:
> + tcg_single = read_fp_sreg(s, rn);
> + switch (out) {
> + case MO_64 | MO_SIGN:
> + gen_helper_vfp_tosqs(tcg_out, tcg_single, tcg_shift,
> tcg_fpstatus);
> + break;
> + case MO_64:
> + gen_helper_vfp_touqs(tcg_out, tcg_single, tcg_shift,
> tcg_fpstatus);
> + break;
> + case MO_32 | MO_SIGN:
> + gen_helper_vfp_tosls(tcg_single, tcg_single,
> + tcg_shift, tcg_fpstatus);
> + tcg_gen_extu_i32_i64(tcg_out, tcg_single);
> + break;
> + case MO_32:
> + gen_helper_vfp_touls(tcg_single, tcg_single,
> + tcg_shift, tcg_fpstatus);
> + tcg_gen_extu_i32_i64(tcg_out, tcg_single);
> + break;
> + default:
> + g_assert_not_reached();
> + }
> + break;
> +
> + case MO_16:
> + tcg_single = read_fp_hreg(s, rn);
> + switch (out) {
> + case MO_64 | MO_SIGN:
> + gen_helper_vfp_tosqh(tcg_out, tcg_single, tcg_shift,
> tcg_fpstatus);
> + break;
> + case MO_64:
> + gen_helper_vfp_touqh(tcg_out, tcg_single, tcg_shift,
> tcg_fpstatus);
> + break;
> + case MO_32 | MO_SIGN:
> + gen_helper_vfp_toslh(tcg_single, tcg_single,
> + tcg_shift, tcg_fpstatus);
> + tcg_gen_extu_i32_i64(tcg_out, tcg_single);
> + break;
> + case MO_32:
> + gen_helper_vfp_toulh(tcg_single, tcg_single,
> + tcg_shift, tcg_fpstatus);
> + tcg_gen_extu_i32_i64(tcg_out, tcg_single);
> + break;
> + default:
> + g_assert_not_reached();
> + }
> + break;
> +
> + default:
> + g_assert_not_reached();
> + }
> +
> + gen_restore_rmode(tcg_rmode, tcg_fpstatus);
> +}
> +
> +static bool do_fcvt_g(DisasContext *s, arg_fcvt *a,
> + ARMFPRounding rmode, bool is_signed)
> +{
> + TCGv_i64 tcg_int;
> + int check = fp_access_check_scalar_hsd(s, a->esz);
> +
> + if (check <= 0) {
> + return check == 0;
> + }
> +
> + tcg_int = cpu_reg(s, a->rd);
> + do_fcvt_scalar(s, (a->sf ? MO_64 : MO_32) | (is_signed ? MO_SIGN : 0),
> + a->esz, tcg_int, a->shift, a->rn, rmode);
> +
> + if (!a->sf) {
> + tcg_gen_ext32u_i64(tcg_int, tcg_int);
For the MO_16 and MO_32 input cases we already did a
zero-extend-to-64-bits inside do_fcvt_scalar().
Maybe we should put the tcg_gen_ext32u_i64() also
inside do_fcvt_scalar() in the cases of MO_64 input
MO_32 output which are the only ones that actually need it?
Otherwise
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
thanks
-- PMM
