From: Hendrik Wüthrich <whend...@google.com>
Implement rdmsr and wrmsr for the following MSRs:
* MSR_IA32_PQR_ASSOC
* MSR_IA32_QM_EVTSEL
* MSR_IA32_QM_CTR
* IA32_L3_QOS_Mask_n
* IA32_L2_QOS_Mask_n
* IA32_L2_QoS_Ext_BW_Thrtl_n
This allows for the guest to call RDT-internal functions to
associate an RMID with a CLOSID / set an active RMID for
monitoring, read monitoring data, and set classes of service.
Signed-off-by: Hendrik Wüthrich <whend...@google.com>
---
hw/i386/rdt.c | 4 ++
include/hw/i386/rdt.h | 4 ++
target/i386/cpu.h | 14 +++++
target/i386/tcg/sysemu/misc_helper.c | 81 ++++++++++++++++++++++++++++
4 files changed, 103 insertions(+)
diff --git a/hw/i386/rdt.c b/hw/i386/rdt.c
index 01bee79cbe..3a37341bd6 100644
--- a/hw/i386/rdt.c
+++ b/hw/i386/rdt.c
@@ -81,6 +81,10 @@ struct RDTState {
struct RDTStateClass {
};
+uint32_t rdt_get_cpuid_10_1_edx_cos_max(void) { return RDT_MAX_L3_MASK_COUNT; }
+uint32_t rdt_get_cpuid_10_2_edx_cos_max(void) { return RDT_MAX_L2_MASK_COUNT; }
+uint32_t rdt_get_cpuid_10_3_edx_cos_max(void) { return
RDT_MAX_MBA_THRTL_COUNT; }
+
bool rdt_associate_rmid_cos(uint64_t msr_ia32_pqr_assoc)
{
X86CPU *cpu = X86_CPU(current_cpu);
diff --git a/include/hw/i386/rdt.h b/include/hw/i386/rdt.h
index 14b1c64b72..ec82a149f2 100644
--- a/include/hw/i386/rdt.h
+++ b/include/hw/i386/rdt.h
@@ -25,6 +25,10 @@ typedef struct RDTStatePerCore RDTStatePerCore;
typedef struct RDTMonitor RDTMonitor;
typedef struct RDTAllocation RDTAllocation;
+uint32_t rdt_get_cpuid_10_1_edx_cos_max(void);
+uint32_t rdt_get_cpuid_10_2_edx_cos_max(void);
+uint32_t rdt_get_cpuid_10_3_edx_cos_max(void);
+
bool rdt_associate_rmid_cos(uint64_t msr_ia32_pqr_assoc);
void rdt_write_msr_l3_mask(uint32_t pos, uint32_t val);
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 0f73c1244d..64a53efa30 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -576,6 +576,17 @@ typedef enum X86Seg {
#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
#define MSR_IA32_VMX_VMFUNC 0x00000491
+#define MSR_IA32_QM_EVTSEL 0x0c8d
+#define MSR_IA32_QM_CTR 0x0c8e
+#define MSR_IA32_PQR_ASSOC 0x0c8f
+
+#define MSR_IA32_L3_CBM_BASE 0x0c90
+#define MSR_IA32_L3_MASKS_END 0x0d0f
+#define MSR_IA32_L2_CBM_BASE 0x0d10
+#define MSR_IA32_L2_CBM_END 0x0d4f
+#define MSR_IA32_L2_QOS_Ext_BW_Thrtl_BASE 0xd50
+#define MSR_IA32_L2_QOS_Ext_BW_Thrtl_END 0xd8f
+
#define MSR_APIC_START 0x00000800
#define MSR_APIC_END 0x000008ff
@@ -1839,6 +1850,9 @@ typedef struct CPUArchState {
uint64_t msr_ia32_feature_control;
uint64_t msr_ia32_sgxlepubkeyhash[4];
+ uint64_t msr_ia32_qm_evtsel;
+ uint64_t msr_ia32_pqr_assoc;
+
uint64_t msr_fixed_ctr_ctrl;
uint64_t msr_global_ctrl;
uint64_t msr_global_status;
diff --git a/target/i386/tcg/sysemu/misc_helper.c
b/target/i386/tcg/sysemu/misc_helper.c
index 094aa56a20..a6c6b11a29 100644
--- a/target/i386/tcg/sysemu/misc_helper.c
+++ b/target/i386/tcg/sysemu/misc_helper.c
@@ -25,6 +25,7 @@
#include "exec/address-spaces.h"
#include "exec/exec-all.h"
#include "tcg/helper-tcg.h"
+#include "hw/i386/rdt.h"
#include "hw/i386/apic.h"
void helper_outb(CPUX86State *env, uint32_t port, uint32_t data)
@@ -293,6 +294,45 @@ void helper_wrmsr(CPUX86State *env)
env->msr_bndcfgs = val;
cpu_sync_bndcs_hflags(env);
break;
+ case MSR_IA32_QM_EVTSEL:
+ env->msr_ia32_qm_evtsel = val;
+ break;
+ case MSR_IA32_PQR_ASSOC:
+ env->msr_ia32_pqr_assoc = val;
+
+ if (!rdt_associate_rmid_cos(val))
+ goto error;
+ break;
+ case MSR_IA32_L3_CBM_BASE ... MSR_IA32_L3_MASKS_END:
+ {
+ uint32_t pos = (uint32_t)env->regs[R_ECX] - MSR_IA32_L3_CBM_BASE;
+
+ if (pos > rdt_get_cpuid_10_1_edx_cos_max()) {
+ goto error;
+ }
+ rdt_write_msr_l3_mask(pos, val);
+ break;
+ }
+ case MSR_IA32_L2_CBM_BASE ... MSR_IA32_L2_CBM_END:
+ {
+ uint32_t pos = (uint32_t)env->regs[R_ECX] - MSR_IA32_L2_CBM_BASE;
+
+ if (pos > rdt_get_cpuid_10_2_edx_cos_max()) {
+ goto error;
+ }
+ rdt_write_msr_l2_mask(pos, val);
+ break;
+ }
+ case MSR_IA32_L2_QOS_Ext_BW_Thrtl_BASE ...
MSR_IA32_L2_QOS_Ext_BW_Thrtl_END:
+ {
+ uint32_t pos = (uint32_t)env->regs[R_ECX] -
MSR_IA32_L2_QOS_Ext_BW_Thrtl_BASE;
+
+ if (pos > rdt_get_cpuid_10_3_edx_cos_max()) {
+ goto error;
+ }
+ rdt_write_mba_thrtl(pos, val);
+ break;
+ }
case MSR_APIC_START ... MSR_APIC_END: {
int ret;
int index = (uint32_t)env->regs[R_ECX] - MSR_APIC_START;
@@ -472,6 +512,47 @@ void helper_rdmsr(CPUX86State *env)
val = (cs->nr_threads * cs->nr_cores) | (cs->nr_cores << 16);
break;
}
+ case MSR_IA32_QM_CTR:
+ val = rdt_read_event_count(x86_cpu->rdt,
+ (env->msr_ia32_qm_evtsel >> 32) & 0xff,
+ env->msr_ia32_qm_evtsel & 0xff);
+ break;
+ case MSR_IA32_QM_EVTSEL:
+ val = env->msr_ia32_qm_evtsel;
+ break;
+ case MSR_IA32_PQR_ASSOC:
+ val = env->msr_ia32_pqr_assoc;
+ break;
+ case MSR_IA32_L3_CBM_BASE ... MSR_IA32_L3_MASKS_END:
+ {
+ uint32_t pos = (uint32_t)env->regs[R_ECX] - MSR_IA32_L3_CBM_BASE;
+
+ if (pos >= rdt_get_cpuid_10_1_edx_cos_max()) {
+ raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC());
+ }
+ val = rdt_read_l3_mask(pos);
+ break;
+ }
+ case MSR_IA32_L2_CBM_BASE ... MSR_IA32_L2_CBM_END:
+ {
+ uint32_t pos = (uint32_t)env->regs[R_ECX] - MSR_IA32_L2_CBM_BASE;
+
+ if (pos >= rdt_get_cpuid_10_2_edx_cos_max()) {
+ raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC());
+ }
+ val = rdt_read_l2_mask(pos);
+ break;
+ }
+ case MSR_IA32_L2_QOS_Ext_BW_Thrtl_BASE ...
MSR_IA32_L2_QOS_Ext_BW_Thrtl_END:
+ {
+ uint32_t pos = (uint32_t)env->regs[R_ECX] -
MSR_IA32_L2_QOS_Ext_BW_Thrtl_BASE;
+
+ if (pos >= rdt_get_cpuid_10_3_edx_cos_max()) {
+ raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC());
+ }
+ val = rdt_read_mba_thrtl(pos);
+ break;
+ }
case MSR_APIC_START ... MSR_APIC_END: {
int ret;
int index = (uint32_t)env->regs[R_ECX] - MSR_APIC_START;
--
2.47.0.338.g60cca15819-goog
