On Wed, Nov 20, 2024 at 12:50 AM Sai Pavan Boddu <[email protected]> wrote: > > Add a basic board with interrupt controller (intc), timer, serial > (uartlite), small memory called LMB@0 (128kB) and DDR@0x80000000 > (configured via command line eg. -m 2g). > This is basic configuration which matches HW generated out of AMD Vivado > (design tools). But initial configuration is going beyond what it is > configured by default because validation should be done on other > configurations too. That's why wire also additional uart16500, axi > ethernet(with axi dma). > GPIOs, i2c and qspi is also listed for completeness. > > IRQ map is: (addr) > 0 - timer (0x41c00000) > 1 - uartlite (0x40600000) > 2 - i2c (0x40800000) > 3 - qspi (0x44a00000) > 4 - uart16550 (0x44a10000) > 5 - emaclite (0x40e00000) > 6 - timer2 (0x41c10000) > 7 - axi emac (0x40c00000) > 8 - axi dma (0x41e00000) > 9 - axi dma > 10 - gpio (0x40000000) > 11 - gpio2 (0x40010000) > 12 - gpio3 (0x40020000) > > Signed-off-by: Sai Pavan Boddu <[email protected]> > Signed-off-by: Michal Simek <[email protected]> > --- > Changes for V2: > Make changes to support -cpu switch > Remove setting of default board > Include doc to toctree > Remove setting of 'imac' extensions as they are available by > default. > Chages for V3: > Replace virt with generic > Update doc with supported riscv extensions > Change base CPU to TYPE_RISCV_CPU_BASE > Changes for V4: > Improved the doc based on comments > Disabled support for Double-Precision and Hypervisor extensions > Updated Maintainers file at riscv machine space. > > MAINTAINERS | 6 + > docs/system/riscv/microblaze-v-generic.rst | 42 +++++ > docs/system/target-riscv.rst | 1 + > hw/riscv/microblaze-v-generic.c | 184 +++++++++++++++++++++ > hw/riscv/Kconfig | 8 + > hw/riscv/meson.build | 1 +
It looks like this needs a rebase, do you mind rebasing on https://github.com/alistair23/qemu/tree/riscv-to-apply.next and sending a new version Alistair
