On 18/11/24 06:07, Alistair Francis wrote:
On Tue, Nov 5, 2024 at 3:43 AM Sai Pavan Boddu <sai.pavan.bo...@amd.com> wrote:
Add a basic board with interrupt controller (intc), timer, serial
(uartlite), small memory called LMB@0 (128kB) and DDR@0x80000000
(configured via command line eg. -m 2g).
This is basic configuration which matches HW generated out of AMD Vivado
(design tools). But initial configuration is going beyond what it is
configured by default because validation should be done on other
configurations too. That's why wire also additional uart16500, axi
ethernet(with axi dma).
GPIOs, i2c and qspi is also listed for completeness.
IRQ map is: (addr)
0 - timer (0x41c00000)
1 - uartlite (0x40600000)
2 - i2c (0x40800000)
3 - qspi (0x44a00000)
4 - uart16550 (0x44a10000)
5 - emaclite (0x40e00000)
6 - timer2 (0x41c10000)
7 - axi emac (0x40c00000)
8 - axi dma (0x41e00000)
9 - axi dma
10 - gpio (0x40000000)
11 - gpio2 (0x40010000)
12 - gpio3 (0x40020000)
Signed-off-by: Sai Pavan Boddu <sai.pavan.bo...@amd.com>
Signed-off-by: Michal Simek <michal.si...@amd.com>
Reviewed-by: Francisco Iglesias <francisco.igles...@amd.com>
---
Changes for V2:
Make changes to support -cpu switch
Remove setting of default board
Include doc to toctree
Remove setting of 'imac' extensions as they are available by
default.
Chages for V3:
Replace virt with generic
Update doc with supported riscv extensions
Change base CPU to TYPE_RISCV_CPU_BASE
MAINTAINERS | 6 +
docs/system/riscv/microblaze-v-generic.rst | 45 +++++
docs/system/target-riscv.rst | 1 +
hw/riscv/microblaze-v-generic.c | 182 +++++++++++++++++++++
hw/riscv/Kconfig | 8 +
hw/riscv/meson.build | 1 +
6 files changed, 243 insertions(+)
create mode 100644 docs/system/riscv/microblaze-v-generic.rst
create mode 100644 hw/riscv/microblaze-v-generic.c
diff --git a/docs/system/riscv/microblaze-v-generic.rst
b/docs/system/riscv/microblaze-v-generic.rst
new file mode 100644
index 00000000000..71e9e655f66
--- /dev/null
+++ b/docs/system/riscv/microblaze-v-generic.rst
@@ -0,0 +1,45 @@
+Microblaze-V generic board (``amd-microblaze-v-generic``)
+=========================================================
+The AMD MicroBlaze™ V processor is a soft-core RISC-V processor IP for AMD
adaptive SoCs and FPGAs.
+The MicroBlaze V processor is based on a 32-bit / 64-bit RISC-V instruction
set architecture (ISA)
+and its fully hardware compatible with the classic MicroBlaze processor.
I'm not sure "fully hardware compatible" is the right thing to say
here as it's a different ISA.
I'm also confused. "fully hardware compatible" seems extracted from
a sales speech. Maybe clarify mentioning 'peripherals'?
Maybe just say that it works with the existing Microblaze IP
+
+More details here:
+https://docs.amd.com/r/en-US/ug1629-microblaze-v-user-guide/MicroBlaze-V-Architecture
+
+The microblaze-v generic board in QEMU has following supported devices
The supported devices should probably be listed here
+
+Implemented devices:
+
+ - timer
+ - uartlite
+ - uart16550
+ - emaclite
+ - timer2
+ - axi emac
+ - axi dma
