[PATCH v2 06/54] accel/tcg: Assert non-zero length in tlb_flush_range_by_mmuidx*

[Richard Henderson]

Next patches will assume non-zero length.

Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
---
 accel/tcg/cputlb.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 77b972fd93..1346a26d90 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -791,6 +791,7 @@ void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr,
     TLBFlushRangeData d;
 
     assert_cpu_is_self(cpu);
+    assert(len != 0);
 
     /*
      * If all bits are significant, and len is small,
@@ -830,6 +831,8 @@ void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState 
*src_cpu,
     TLBFlushRangeData d, *p;
     CPUState *dst_cpu;
 
+    assert(len != 0);
+
     /*
      * If all bits are significant, and len is small,
      * this devolves to tlb_flush_page.
-- 
2.43.0