From: Nicholas Piggin <npig...@gmail.com>
POWER8 does not have the ISA IRQ -> SERIRQ routing system of later
CPUs, instead all ISA IRQs are sent to the CPU via a single PSI
interrupt. There is a sanity check in the POWER8 case to ensure the
routing bits have not been set, because that would indicate a
programming error.
Those bits were incorrectly specified because of ppc bit numbering
fun. Coverity detected this as an always-zero expression.
Cc: qemu-sta...@nongnu.org
Reported-by: Cédric Le Goater <c...@redhat.com>
Resolves: Coverity CID 1558829 (partially)
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
(cherry picked from commit 84416e262ea1218026a8567ed9ea31c16d77edea)
Signed-off-by: Michael Tokarev <m...@tls.msk.ru>
diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c
index 80b79dfbbc..8c203d2059 100644
--- a/hw/ppc/pnv_lpc.c
+++ b/hw/ppc/pnv_lpc.c
@@ -427,8 +427,8 @@ static void pnv_lpc_eval_serirq_routes(PnvLpcController
*lpc)
int irq;
if (!lpc->psi_has_serirq) {
- if ((lpc->opb_irq_route0 & PPC_BITMASK(8, 13)) ||
- (lpc->opb_irq_route1 & PPC_BITMASK(4, 31))) {
+ if ((lpc->opb_irq_route0 & PPC_BITMASK32(8, 13)) ||
+ (lpc->opb_irq_route1 & PPC_BITMASK32(4, 31))) {
qemu_log_mask(LOG_GUEST_ERROR,
"OPB: setting serirq routing on POWER8 system, ignoring.\n");
}
--
2.39.5
