On 29/10/24 06:17, Jamin Lin wrote:
The size of SDHCI capabilities register is 64bits, so introduces new Capabilities Register 2 for SD slot 0 (0x144) and SD slot1 (0x244).Signed-off-by: Jamin Lin <jamin_...@aspeedtech.com> --- hw/sd/aspeed_sdhci.c | 40 +++++++++++++++++++++++++++++----------- 1 file changed, 29 insertions(+), 11 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
