This patchseries refactors the target-arm handling of coprocessor registers so that you define each register with a struct (and possibly some read/write/reset functions), rather than having huge nested switch statements in get_cp15()/set_cp15().
My main aim here was to get rid of the unmaintainable switch statements. The series also removes all the "behaviour depends on value of main ID register" code by a combination of defining implementation-specific cp15 regs in the implementation subclass instance init functions, and some extra feature bits. As well as get/set_cp15, we also can remove the rather limited existing effort at "define a cp register" used by the pxa2xx boards, and the framework has 64 bit register support which should provide a nice clean base to implement LPAE registers. Patch 1 defines all the new infrastructure/framework, while leaving the old functions in place. The remaining patches convert small subsets of the cp registers, until everything has moved over and the old functions can be deleted. The conversion functions mostly take the approach of preserving the old QEMU behaviour even if it's not really right. However in some cases I have tightened up behaviour where it was both obviously wrong and painful to reproduce the same brokenness in the new scheme. I've generally remarked on those cases in the individual commit comments. I wanted to squeeze this in before the soft freeze deadline, so there might be a few rough edges. We can make a decision about whether it actually makes sense to commit before hardfreeze depending on how the review phase goes. The patchseries sits on top of the 'drop cpu_reset_model_id()' v2 patchset I sent out yesterday. The whole thing is available in git at: git://git.linaro.org/people/pmaydell/qemu-arm.git cp15-on-qom-on-miniqom and pointy-clicky web version: http://git.linaro.org/gitweb?p=people/pmaydell/qemu-arm.git;a=shortlog;h=refs/heads/cp15-on-qom-on-miniqom thanks -- PMM Peter Maydell (32): target-arm: initial coprocessor register framework hw/pxa2xx: Convert cp14 perf registers to new scheme hw/pxa2xx.c: Convert CLKCFG and PWRMODE cp14 regs hw/pxa2xx_pic: Convert coprocessor registers to new scheme target-arm: Remove old cpu_arm_set_cp_io infrastructure target-arm: Add register_cp_regs_for_features() target-arm: Convert debug registers to cp_reginfo target-arm: Convert TEECR, TEEHBR to new scheme target-arm: Convert WFI/barriers special cases to cp_reginfo target-arm: Convert TLS registers target-arm: Convert performance monitor registers target-arm: Convert generic timer cp15 regs target-arm: Convert cp15 c3 register target-arm: Convert MMU fault status cp15 registers target-arm: Convert cp15 crn=2 registers target-arm: Convert cp15 crn=13 registers target-arm: Convert cp15 crn=10 registers target-arm: Convert cp15 crn=15 registers target-arm: Convert cp15 MMU TLB control target-arm: Convert cp15 VA-PA translation registers target-arm: convert cp15 crn=7 registers target-arm: Convert cp15 crn=6 registers target-arm: Convert cp15 crn=9 registers target-arm: Convert cp15 crn=1 registers target-arm: Convert cp15 crn=0 crm={1,2} feature registers target-arm: Convert cp15 cache ID registers target-arm: Convert MPIDR target-arm: Convert final ID registers target-arm: Remove c0_cachetype CPUARMState field target-arm: Move block cache ops to new cp15 framework target-arm: Remove remaining old cp15 infrastructure target-arm: Remove ARM_CPUID_* macros hw/pxa2xx.c | 285 +++---- hw/pxa2xx_pic.c | 53 +- linux-user/cpu-uname.c | 5 +- target-arm/cpu-qom.h | 2 + target-arm/cpu.c | 220 ++++-- target-arm/cpu.h | 261 ++++++- target-arm/helper.c | 2046 ++++++++++++++++++++++++++--------------------- target-arm/helper.h | 11 +- target-arm/machine.c | 2 - target-arm/op_helper.c | 42 +- target-arm/translate.c | 473 ++++-------- 11 files changed, 1865 insertions(+), 1535 deletions(-)
