The following changes since commit f774a677507966222624a9b2859f06ede7608100:
Merge tag 'pull-target-arm-20241015-1' of https://git.linaro.org/people/pmaydell/qemu-arm into staging (2024-10-15 15:18:22 +0100) are available in the Git repository at: https://gitlab.com/bonzini/qemu.git tags/for-upstream for you to fetch changes up to 15d955975bd484c2c66af0d6daaa02a7d04d2256: target/i386: Use only 16 and 32-bit operands for IN/OUT (2024-10-17 19:41:30 +0200) ---------------------------------------------------------------- * tcg/s390x: Fix for TSTEQ/TSTNE * target/i386: Fixes for IN and OUT with REX prefix * target/i386: New CPUID features and logic fixes * target/i386: Add support save/load HWCR MSR * target/i386: Move more instructions to new decoder; separate decoding and IR generation * target/i386/tcg: Use DPL-level accesses for interrupts and call gates * accel/kvm: perform capability checks on VM file descriptor when necessary * accel/kvm: dynamically sized kvm memslots array * target/i386: fixes for Hyper-V * docs/system: Add recommendations to Hyper-V enlightenments doc ---------------------------------------------------------------- v1->v2: new patch to fix tcg/s390x mark new patch and "check for KVM_CAP_READONLY_MEM on VM" for stable Chao Gao (1): target/i386: Add more features enumerated by CPUID.7.2.EDX Gao Shiyuan (1): target/i386: Add support save/load HWCR MSR Paolo Bonzini (10): tcg/s390x: fix constraint for 32-bit TSTEQ/TSTNE target/i386: convert bit test instructions to new decoder target/i386: decode address before going back to translate.c target/i386: convert CMPXCHG8B/CMPXCHG16B to new decoder target/i386: do not check PREFIX_LOCK in old-style decoder target/i386: list instructions still in translate.c target/i386: assert that cc_op* and pc_save are preserved target/i386/tcg: Use DPL-level accesses for interrupts and call gates accel/kvm: check for KVM_CAP_MULTI_ADDRESS_SPACE on vm accel/kvm: check for KVM_CAP_MEMORY_ATTRIBUTES on vm Peter Xu (4): KVM: Dynamic sized kvm memslots array KVM: Define KVM_MEMSLOTS_NUM_MAX_DEFAULT KVM: Rename KVMMemoryListener.nr_used_slots to nr_slots_used KVM: Rename KVMState->nr_slots to nr_slots_max Richard Henderson (1): target/i386: Use only 16 and 32-bit operands for IN/OUT Tom Dohrmann (1): accel/kvm: check for KVM_CAP_READONLY_MEM on VM Vitaly Kuznetsov (4): target/i386: Fix conditional CONFIG_SYNDBG enablement target/i386: Exclude 'hv-syndbg' from 'hv-passthrough' target/i386: Make sure SynIC state is really updated before KVM_RUN docs/system: Add recommendations to Hyper-V enlightenments doc Xiaoyao Li (4): target/i386: Don't construct a all-zero entry for CPUID[0xD 0x3f] target/i386: Enable fdp-excptn-only and zero-fcs-fds target/i386: Construct CPUID 2 as stateful iff times > 1 target/i386: Make invtsc migratable when user sets tsc-khz explicitly docs/system/i386/hyperv.rst | 43 +++- include/sysemu/kvm_int.h | 7 +- target/i386/cpu.h | 9 + target/i386/tcg/decode-new.h | 19 +- accel/kvm/kvm-all.c | 131 ++++++++---- target/i386/cpu.c | 21 +- target/i386/kvm/hyperv.c | 1 + target/i386/kvm/kvm.c | 47 +++-- target/i386/machine.c | 20 ++ target/i386/tcg/seg_helper.c | 17 +- target/i386/tcg/translate.c | 444 ++++++--------------------------------- target/i386/tcg/decode-new.c.inc | 145 +++++++++---- target/i386/tcg/emit.c.inc | 246 +++++++++++++++++++++- tcg/s390x/tcg-target.c.inc | 24 ++- accel/kvm/trace-events | 1 + 15 files changed, 682 insertions(+), 493 deletions(-) -- 2.46.2 From: Paolo Bonzini <pbonz...@redhat.com> Date: Thu, 17 Oct 2024 11:09:52 +0200 Subject: [PULL 11/26] tcg/s390x: fix constraint for 32-bit TSTEQ/TSTNE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit 32-bit TSTEQ and TSTNE is subject to the same constraints as for 64-bit, but setcond_i32 and negsetcond_i32 were incorrectly using TCG_CT_CONST ("i") instead of TCG_CT_CONST_CMP ("C"). Adjust the constraint and make tcg_target_const_match use the same sequence as tgen_cmp2: first check if the constant is a valid operand for TSTEQ/TSTNE, then accept everything for 32-bit non-test comparisons, finally check if the constant is a valid operand for 64-bit non-test comparisons. Reported-by: Philippe Mathieu-Daudé <phi...@linaro.org> Cc: qemu-sta...@nongnu.org Signed-off-by: Paolo Bonzini <pbonz...@redhat.com> --- tcg/s390x/tcg-target.c.inc | 24 ++++++++++++++++-------- 1 file changed, 16 insertions(+), 8 deletions(-) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index a5d57197a4b..27bccc14e50 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -565,6 +565,20 @@ static bool tcg_target_const_match(int64_t val, int ct, } if (ct & TCG_CT_CONST_CMP) { + if (is_tst_cond(cond)) { + if (is_const_p16(uval) >= 0) { + return true; /* TMxx */ + } + if (risbg_mask(uval)) { + return true; /* RISBG */ + } + return false; + } + + if (type == TCG_TYPE_I32) { + return true; + } + switch (cond) { case TCG_COND_EQ: case TCG_COND_NE: @@ -584,13 +598,7 @@ static bool tcg_target_const_match(int64_t val, int ct, break; case TCG_COND_TSTNE: case TCG_COND_TSTEQ: - if (is_const_p16(uval) >= 0) { - return true; /* TMxx */ - } - if (risbg_mask(uval)) { - return true; /* RISBG */ - } - break; + /* checked above, fallthru */ default: g_assert_not_reached(); } @@ -3231,9 +3239,9 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_rotl_i64: case INDEX_op_rotr_i32: case INDEX_op_rotr_i64: + return C_O1_I2(r, r, ri); case INDEX_op_setcond_i32: case INDEX_op_negsetcond_i32: - return C_O1_I2(r, r, ri); case INDEX_op_setcond_i64: case INDEX_op_negsetcond_i64: return C_O1_I2(r, r, rC); -- 2.46.2
