Re: [PATCH v7 2/5] target/riscv: Handle Smrnmi interrupt and exception

[Clément Léger]

On 14/10/2024 20:19, frank.ch...@sifive.com wrote:
> @@ -1679,6 +1718,20 @@ void riscv_cpu_do_interrupt(CPUState *cs)
>      target_ulong mtval2 = 0;
>      int sxlen = 0;
>      int mxlen = 0;
> + bool nnmi_excep = false;
> +
> + if (cpu->cfg.ext_smrnmi && env->rnmip && async) {
> + env->mnstatus = set_field(env->mnstatus, MNSTATUS_NMIE, false);
> + env->mnstatus = set_field(env->mnstatus, MNSTATUS_MNPV,
> + env->virt_enabled);
> + env->mnstatus = set_field(env->mnstatus, MNSTATUS_MNPP,
> + env->priv);
> + env->mncause = cause | ((target_ulong)1U << (TARGET_LONG_BITS - 1));
> + env->mnepc = env->pc;
> + env->pc = env->rnmi_irqvec;
> + riscv_cpu_set_mode(env, PRV_M, virt);

Hi Frank,

Does it make sense to use the virt value here since if we are going to
PRV_M mode, then virt should be false ?

Thanks,

Clément


> + return;
> + }