On Wed, 2 Oct 2024 at 06:51, Alistair Francis <alistai...@gmail.com> wrote: > > The following changes since commit 718780d20470c66a3a36d036b29148d5809dc855: > > Merge tag 'pull-nvme-20241001' of https://gitlab.com/birkelund/qemu into > staging (2024-10-01 11:34:07 +0100) > > are available in the Git repository at: > > https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20241002 > > for you to fetch changes up to 74b493244d0624afed22606e76fc7fca62777401: > > bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files > (2024-10-02 15:11:52 +1000) > > ---------------------------------------------------------------- > RISC-V PR for 9.2 > > * Add a property to set vl to ceil(AVL/2) > * Enable numamem testing for RISC-V > * Consider MISA bit choice in implied rule > * Fix the za64rs priv spec requirements > * Enable Bit Manip for OpenTitan Ibex CPU > * Fix the group bit setting of AIA with KVM > * Stop timer with infinite timecmp > * Add 'fcsr' register to QEMU log as a part of F extension > * Fix riscv64 build on musl libc > * Add preliminary textra trigger CSR functions > * RISC-V bsd-user support > * Respect firmware ELF entry point > * Add Svvptc extension support > * Fix masking of rv32 physical address > * Fix linking problem with semihosting disabled > * Fix IMSIC interrupt state updates
Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/9.2 for any user-visible changes. -- PMM
