Re: [PULL v2 16/47] hw/riscv: add RISC-V IOMMU base emulation

[Daniel Henrique Barboza]

On 10/1/24 7:24 PM, Tomasz Jeznach wrote:

On Tue, Sep 24, 2024 at 3:18 PM Alistair Francis <alistai...@gmail.com> wrote:

+
+/* IOMMU index for transactions without process_id specified. */
+#define RISCV_IOMMU_NOPROCID 0
+
+static uint8_t riscv_iommu_get_icvec_vector(uint32_t icvec, uint32_t vec_type)
+{
+    switch (vec_type) {
+    case RISCV_IOMMU_INTR_CQ:
+        return icvec & RISCV_IOMMU_ICVEC_CIV;
+    case RISCV_IOMMU_INTR_FQ:
+        return icvec & RISCV_IOMMU_ICVEC_FIV >> 4;

Please add missing brackets to fix operator ordering bug. Here and for
PM, PQ cases.
It should be:  return (icvec & RISCV_IOMMU_ICVEC_FIV) >> 4

Nice catch. Changed in v8. Thanks,


Daniel

+    case RISCV_IOMMU_INTR_PM:
+        return icvec & RISCV_IOMMU_ICVEC_PMIV >> 8;
+    case RISCV_IOMMU_INTR_PQ:
+        return icvec & RISCV_IOMMU_ICVEC_PIV >> 12;
+    default:
+        g_assert_not_reached();
+    }
+}
+

thanks,
- Tomasz