Re: [PATCH 05/13] hw/mips: Add cpu_is_bigendian field to BlCpuCfg structure

[Pierrick Bouvier]

On 9/30/24 00:34, Philippe Mathieu-Daudé wrote:

Add the BlCpuCfg::cpu_is_bigendian field, initialize it in
machine code. Bootloader API use the ld/st_endian_p() to
dispatch to target endianness.

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
---
  include/hw/mips/bootloader.h |  1 +
  hw/mips/bootloader.c         | 10 +++++-----
  hw/mips/boston.c             |  2 +-
  hw/mips/fuloong2e.c          |  2 +-
  hw/mips/malta.c              |  2 +-
  5 files changed, 9 insertions(+), 8 deletions(-)

diff --git a/include/hw/mips/bootloader.h b/include/hw/mips/bootloader.h
index 744eb11d0e..ef778a38d0 100644
--- a/include/hw/mips/bootloader.h
+++ b/include/hw/mips/bootloader.h
@@ -13,6 +13,7 @@
  #include "exec/target_long.h"

typedef struct bl_cpu_cfg {

+    bool cpu_is_bigendian;
  } BlCpuCfg;

void bl_gen_jump_to(const BlCpuCfg *cfg, void **p, target_ulong jump_addr);

diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
index ee1a1c4f20..258cc5d8c8 100644
--- a/hw/mips/bootloader.c
+++ b/hw/mips/bootloader.c
@@ -58,9 +58,9 @@ static void st_nm32_p(const BlCpuCfg *cfg, void **ptr, 
uint32_t insn)
  {
      uint16_t *p = *ptr;

- stw_p(p, insn >> 16);

+    stw_endian_p(cfg->cpu_is_bigendian, p, insn >> 16);
      p++;
-    stw_p(p, insn >> 0);
+    stw_endian_p(cfg->cpu_is_bigendian, p, insn >> 0);
      p++;

*ptr = p;

@@ -74,7 +74,7 @@ static void bl_gen_nop(const BlCpuCfg *cfg, void **ptr)
      } else {
          uint32_t *p = *ptr;

- stl_p(p, 0);

+        stl_endian_p(cfg->cpu_is_bigendian, p, 0);
          p++;
          *ptr = p;
      }
@@ -95,7 +95,7 @@ static void bl_gen_r_type(const BlCpuCfg *cfg,
      insn = deposit32(insn, 6, 5, shift);
      insn = deposit32(insn, 0, 6, funct);

- stl_p(p, insn);

+    stl_endian_p(cfg->cpu_is_bigendian, p, insn);
      p++;

*ptr = p;

@@ -113,7 +113,7 @@ static void bl_gen_i_type(const BlCpuCfg *cfg,
      insn = deposit32(insn, 16, 5, rt);
      insn = deposit32(insn, 0, 16, imm);

- stl_p(p, insn);

+    stl_endian_p(cfg->cpu_is_bigendian, p, insn);
      p++;

*ptr = p;

diff --git a/hw/mips/boston.c b/hw/mips/boston.c
index 8e210876e1..d4dd242d0d 100644
--- a/hw/mips/boston.c
+++ b/hw/mips/boston.c
@@ -325,7 +325,7 @@ type_init(boston_register_types)

static void gen_firmware(void *p, hwaddr kernel_entry, hwaddr fdt_addr)

  {
-    const BlCpuCfg bl_cfg = { };
+    const BlCpuCfg bl_cfg = { .cpu_is_bigendian = TARGET_BIG_ENDIAN };
      uint64_t regaddr;

/* Move CM GCRs */

diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c
index a989637d3b..4fe5108845 100644
--- a/hw/mips/fuloong2e.c
+++ b/hw/mips/fuloong2e.c
@@ -165,7 +165,7 @@ static uint64_t load_kernel(MIPSCPU *cpu)
  static void write_bootloader(CPUMIPSState *env, uint8_t *base,
                               uint64_t kernel_addr)
  {
-    const BlCpuCfg bl_cfg = { };
+    const BlCpuCfg bl_cfg = { .cpu_is_bigendian = false };
      uint32_t *p;

/* Small bootloader */

diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index fc485cc884..6e73c896ff 100644
--- a/hw/mips/malta.c
+++ b/hw/mips/malta.c
@@ -624,7 +624,7 @@ static void bl_setup_gt64120_jump_kernel(void **p, uint64_t 
run_addr,
      static const char pci_pins_cfg[PCI_NUM_PINS] = {
          10, 10, 11, 11 /* PIIX IRQRC[A:D] */
      };
-    const BlCpuCfg bl_cfg = { };
+    const BlCpuCfg bl_cfg = { .cpu_is_bigendian = TARGET_BIG_ENDIAN };

/* Bus endianness is always reversed */

  #if TARGET_BIG_ENDIAN

Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>